M14D5121632A_1 Datasheet, PDF (29/59 Pages) Elite Semiconductor Memory Technology Inc. – 8M x 16 Bit x 4 Banks DDR II SDRAM

ESMT
M14D5121632A
Operation Temperature Condition (TC) -40°C~95°C
OCD Adjustable Mode
CLK
CLK
Command EMRS(1)
WL
DQS, DQS
DQ
DM
NOP
tDS tDH
DT0 DT1 DT2 DT3
EMRS(1)
NOP
tWR
OCD adjustable
OCD calibration mode exit
Note: For proper operation of adjustable mode, WL = RL - 1 = AL + CL - 1 clocks and t_DS / t_DH should be met as the
above timing diagram. For input data pattern for adjustment, DT0 - DT3 is a fixed order and "not affected by
MRS addressing mode (ie. sequential or interleave).
CLK
CLK
Command EMRS(1)
High-Z
DQS, DQS
DQ
tOIT
OCD Driver Mode
NOP
EMRS(1)
DQs high and DQS low for Drive-1, DQs low and DQS high for Drive-0
High-Z
DQs high for Drive-1
DQs low for Drive-0
tOIT
Enter drive mode
OCD Calibration mode exit
Note: Drive mode, both Drive-1 and Drive-0, is used for controllers to measure DDR2 SDRAM driver impedance. In
this mode, all outputs are driven out t_OIT after “enter drive mode” command and all output drivers are
turned-off t_OIT after “OCD calibration mode exit” command as the above timing diagram.
Elite Semiconductor Memory Technology Inc.
Publication Date : Feb. 2009
Revision : 1.1
29/59