M14D5121632A_1 Datasheet, PDF (5/59 Pages) Elite Semiconductor Memory Technology Inc. – 8M x 16 Bit x 4 Banks DDR II SDRAM

ESMT
M14D5121632A
Operation Temperature Condition (TC) -40°C~95°C
Operation Temperature Condition
Parameter
Symbol
Value
Unit
Operation temperature
T_C
-40 ~ +95
°C
Note: 1. Operating temperature is the case surface temperature on the center/top side of the DRAM.
2. Supporting -40 to +85℃ with full AC and DC specifications.
Supporting -40 to + 85℃ and being able to extend to + 95 ℃ with doubling auto-refresh commands in frequency to a
32ms period ( t_REFI = 3.9μs ) and higher temperature Self-Refresh entry via A7 “1” on EMRS(2).
DC Operation Condition & Specifications
DC Operation Condition
(Recommended DC operating conditions)
Parameter
Supply voltage
Supply voltage for DLL
Supply voltage for output
Input reference voltage
Termination voltage (system)
Input logic high voltage
Input logic low voltage
(All voltages referenced to VSS)
Symbol
V_DD
V_DDL
V_DDQ
V_REF
V_TT
V_IH (DC)
V_IL (DC)
Min.
1.7
1.7
1.7
0.49 x V_DDQ
V_REF - 0.04
V_REF + 0.125
-0.3
Typ.
1.8
1.8
1.8
0.5 x V_DDQ
V_REF
-
-
Max.
1.9
1.9
1.9
0.51 x V_DDQ
V_REF + 0.04
V_DDQ + 0.3
V_REF - 0.125
Unit Note
V 4,9
V 4,9
V 4,9
V 1,2,9
V 3,9
V
V
Parameter
Symbol
Value
Unit Note
Minimum required output pull-up under AC test load
V_OH
V_TT + 0.603
V
8
Maximum required output pull-down under AC test load
V_OL
V_TT - 0.603
V
8
Input leakage current
|I _LI|
2
uA
5
Output leakage current
|I _LO|
5
uA
6
Output minimum source DC current ( V_DDQ(min); V_OUT
I _OH
=1.42V )
-13.4
mA 7, 8
Output minimum sink DC current ( V_DDQ(min); V_OUT =
I _OL
0.28V )
+13.4
mA 7, 8
Note:
1. The value of VREF may be selected by the user to provide optimum noise margin in the system. Typically the value of
VREF is expected to be about 0.5 x VDDQ of the transmitting device and VREF is expected to track variations in VDDQ.
2. Peak to peak AC noise on VREF may not exceed ±2% VREF(DC).
3. VTT of transmitting device must track VREF of receiving device.
4. VDDQ and VDDL track VDD. AC parameters are measured with VDD, VDDQ and VDDL tied together.
5. Any input 0V ≤ VIN ≤ VDD; all other balls not under test = 0V.
6. 0V ≤ VOUT ≤ VDDQ; DQ and ODT disabled.
7. The DC value of VREF applied to the receiving device is expected to be set to V_TT.
8. After OCD calibration to 18Ω at T_C = 25℃, VDD = VDDQ = 1.8V.
9. There is no specific device VDD supply voltage requirement for SSTL_18 compliance. However, under all conditions
VDDQ must be less than or equal to VDD.
Elite Semiconductor Memory Technology Inc.
Publication Date : Feb. 2009
Revision : 1.1
5/59