M14D5121632A_1 Datasheet, PDF (6/59 Pages) Elite Semiconductor Memory Technology Inc. – 8M x 16 Bit x 4 Banks DDR II SDRAM

ESMT
M14D5121632A
Operation Temperature Condition (TC) -40°C~95°C
DC Specifications
(IDD values are for the operation range of Voltage and Temperature)
Parameter
Symbol
Test Condition
Version
Unit
-3
One bank;
Operating Current
(Active - Precharge)
IDD0
t_CK = t_CK (IDD), t_RC = t_RC (IDD), t_RAS = t_RAS (IDD)min;
CKE is High, CS is HIGH between valid commands;
Address bus inputs are SWITCHING;
mA
65
Data bus inputs are SWITCHING
One bank; I_OUT = 0mA;
BL = 4, CL = CL(IDD), AL = 0;
Operating Current
t_CK = t_CK (IDD), t_RC = t_RC (IDD),
(Active - Read -
IDD1 t_RAS = t_RAS (IDD)min, t_RCD = t_RCD (IDD);
mA
Precharge)
CKE is HIGH, CS is HIGH between valid commands;
80
Address bus inputs are SWITCHING;
Data pattern is same as IDD4W
Precharge
Power-Down
Standby Current
IDD2P
All banks idle;
t_CK = t_CK (IDD); CKE is LOW;
Other control and address bus inputs are STABLE;
Data bus inputs are FLOATING
mA
10
Precharge Quiet
Standby Current
IDD2Q
All banks idle;
t_CK = t_CK (IDD); CKE is HIGH, CS is HIGH;
Other control and address bus inputs are STABLE;
Data bus inputs are FLOATING
mA
15
All banks idle;
t_CK = t_CK (IDD); CKE is HIGH, CS is HIGH;
Idle Standby Current IDD2N _{Other control and address bus inputs are SWITCHING;}
20
mA
Data bus inputs are SWITCHING
All banks open;
Fast PDN Exit
Active Power-down
Standby Current
IDD3P
t_CK = t_CK (IDD); CKE is LOW;
Other control and address bus inputs
MRS(12) = 0
15
mA
are STABLE;
Slow PDN Exit
Data bus input are FLOATING
MRS(12) = 1
12
All banks open;
Active Standby
Current
IDD3N
t_CK = t_CK (IDD), t_RAS = t_RAS (IDD)max, t_RP = t_RP (IDD);
CKE is HIGH, CS is HIGH between valid commands;
Other control and address bus inputs are SWITCHING;
35
mA
Data bus inputs are SWITCHING
All banks open, continuous burst Reads, I_OUT = 0mA;
BL = 4, CL = CL (IDD), AL = 0;
Operation Current
(Read)
t_CK = t_CK (IDD), t_RAS = t_RAS (IDD)max, t_RP = t_RP (IDD);
IDD4R _{CKE is HIGH, CS is HIGH between valid commands;}
145
mA
Address bus inputs are SWITCHING;
Data pattern is the same as IDD4W;
All banks open, continuous burst Writes;
BL = 4, CL = CL (IDD), AL = 0;
Operation Current
(Write)
t_CK = t_CK (IDD), t_RAS = t_RAS (IDD)max, t_RP = t_RP (IDD);
IDD4W _{CKE is HIGH, CS is HIGH between valid commands;}
140
mA
Address bus inputs are SWITCHING;
Data bus inputs are SWITCHING
Elite Semiconductor Memory Technology Inc.
Publication Date : Feb. 2009
Revision : 1.1
6/59