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M14D5121632A_1 Datasheet, PDF (42/59 Pages) Elite Semiconductor Memory Technology Inc. – 8M x 16 Bit x 4 Banks DDR II SDRAM
ESMT
M14D5121632A
Operation Temperature Condition (TC) -40°C~95°C
Burst Read Followed by Precharge
Minimum Read to Precharge command spacing to the same bank = AL + BL/2 + max(tRTP, 2) - 2 clocks.
For the earliest possible Precharge, the Precharge command may be issued on the rising edge which is “Additive latency (AL) +
BL/2 clocks” after a Read command. A new Bank Active command may be issued to the same bank after the Precharge time (tRP).
A Precharge command cannot be issued until tRAS is satisfied.
The minimum Read to Precharge spacing has also to satisfy a minimum analog time from the rising clock edge that initiates the
last 4-bit prefetch of a Read to Precharge command. This time is called tRTP (Read to Precharge). For BL = 4, this is the time from
the actual read (AL after the Read command) to Precharge command. For BL = 8, this is the time from AL + 2 clocks after the Read
to the Precharge command.
< RL= 4 (AL= 1; CL= 3) >
T0
T1
T2
T3
T4
T5
T6
T7
T8
CLK
CLK
BL = 4
BL = 8
CMD
DQS,DQS
DQs
CMD
DQS,DQS
DQs
Posted CAS
READ A
NOP
NOP
AL + BL/2 clks
Precharge
AL = 1
RL = 4
CL = 3
>= tRAS
>= tRTP
Posted CAS
READ A
NOP
NOP
AL + BL/2 clks
NOP
AL = 1
RL = 4
CL = 3
NOP
NOP
NOP
Bank A
Active
NOP
>= tRP
DoutA0 DoutA1 DoutA2 DoutA3
CL = 3
NOP
Precharge A
NOP
NOP
NOP
DoutA0 DoutA1 DoutA2 DoutA3 DoutA4 DoutA5 DoutA6 DoutA7
>= tRTP
< RL= 5 (AL= 2; CL= 3); BL= 4 >
T0
T1
T2
T3
T4
T5
T6
T7
T8
CLK
CLK
CMD
Posted CAS
READ A
NOP
NOP
AL + BL/2 clks
NOP
Precharge A
NOP
NOP
>= tRP
Bank A
Active
DQS,DQS
DQs
AL = 2
RL = 5
>= tRAS
CL = 3
>= tRTP
DoutA0 DoutA1 DoutA2 DoutA3
CL = 3
< RL= 6 (AL= 2; CL= 4); BL= 4 >
T0
T1
T2
T3
T4
T5
T6
T7
CLK
CLK
NOP
T8
CMD
DQS,DQS
DQs
Posted CAS
READ A
NOP
NOP
AL + BL/2 clks
NOP
Precharge A
AL = 2
>= tRAS
CL = 4
RL = 6
>= tRTP
NOP
NOP
>= tRP
Bank A
Active
NOP
DoutA0 DoutA1 DoutA2 DoutA3
CL = 4
Elite Semiconductor Memory Technology Inc.
Publication Date : Feb. 2009
Revision : 1.1
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