M14D5121632A_1 Datasheet, PDF (43/59 Pages) Elite Semiconductor Memory Technology Inc. – 8M x 16 Bit x 4 Banks DDR II SDRAM

ESMT
M14D5121632A
Operation Temperature Condition (TC) -40°C~95°C
< RL= 4 (AL= 0; CL= 4); BL=8 >
T0
T1
T2
T3
T4
T5
T6
T7
T8
CLK
CLK
CMD
DQS,DQS
DQs
Posted CAS
WRITE A
NOP
NOP
AL+2 clks + max(tRTP;2)
AL = 0
CL = 4
RL = 4
>= tRAS
NOP
NOP Precharg A
NOP
> = tRP
NOP
Bank A
Active
DoutA0 DoutA1 _DoutA2 DoutA3 DoutA4 DoutA5 DoutA6 DoutA7
Burst Write Followed by Precharge
Minimum Write to Precharge command spacing to the same bank = WL + BL/2 clocks + t_WR.
For write cycles, a delay must be satisfied from the completion of the last burst write cycle until the Precharge command can be
issued. This delay is known as a write recovery time (t_WR) referenced from the completion of the Burst Write to the Precharge
command. No Precharge command should be issued prior to the t_WR delay.
CLK
CLK
CMD
DQS,DQS
DQs
< WL= (RL-1) = 3; BL=4>
T0
T1
T2
T3
T4
T5
Posted CAS
WRITE A
NOP
NOP
NOP
NOP
NOP
WL = 3
DinA0 DinA1 DinA2 DinA3
T6
T7
T8
NOP
> = tWR
NOP
Precharg A
CLK
CLK
CMD
DQS,DQS
DQs
< WL= (RL-1) = 4; BL=4 >
T0
T1
T2
T3
T4
T5
T6
T7
T9
Posted CAS
WRITE A
NOP
NOP
NOP
NOP
NOP
NOP
NOP
> = tWR
Precharg A
WL = 4
DinA0 DinA1 DinA2 DinA3
Elite Semiconductor Memory Technology Inc.
Publication Date : Feb. 2009
Revision : 1.1
43/59