M14D5121632A_1 Datasheet, PDF (37/59 Pages) Elite Semiconductor Memory Technology Inc. – 8M x 16 Bit x 4 Banks DDR II SDRAM

ESMT
M14D5121632A
Operation Temperature Condition (TC) -40°C~95°C
Burst Read followed by Burst Write
< RL= 5; WL= (RL-1) = 4; BL= 4 >
T0
CLK
CLK
T1
Tn-1
Tn
Tn+1
Tn+2
Tn+3
Tn+4
Tn+5
CMD
Posted CAS
READ A
DQS,DQS
DQs
NOP
NOP
Posted CAS
WRITE A
tRTW (Read to Write-turn around-time)
NOP
NOP
NOP
NOP
NOP
RL = 5
WL = RL-1 = 4
DoutA0 DoutA1 DoutA2 DoutA3
DinA0 DinA1 DinA2 DinA3
Note: The minimum time from the Burst Read command to the Burst Write command is defined by a read to
write-turn around-time(t_RTW), which is 4 clocks in case of BL = 4 operation, 6 clocks in case of BL = 8
operation.
Seamless Burst Read
CLK
CLK
CMD
< RL= 5; AL= 2; CL= 3; BL = 4 >
T0
T1
T2
T3
T4
T5
T6
T7
T8
Posted CAS
READ A
NOP
Posted CAS
READ B
NOP
NOP
NOP
NOP
NOP
NOP
DQS,DQS
DQs
AL = 2
CL = 3
RL = 5
DoutA0 DoutA1 DoutA2 DoutA3 DoutB0 DoutB1 DoutB2
Note: The seamless burst read operation is supported by enabling a Read command at every other clock for BL =
4 operation, and every 4 clock for BL = 8 operation. This operation is allowed regardless of same or different
banks as long as the banks are activated.
Elite Semiconductor Memory Technology Inc.
Publication Date : Feb. 2009
Revision : 1.1
37/59