M14D5121632A_1 Datasheet, PDF (21/59 Pages) Elite Semiconductor Memory Technology Inc. – 8M x 16 Bit x 4 Banks DDR II SDRAM

ESMT
M14D5121632A
Operation Temperature Condition (TC) -40°C~95°C
Command Truth Table
Register
Refresh
COMMAND
Extended MRS
Mode Register Set
Auto Refresh
Entry
Self
Refresh _Exit
Note 7 Note 7
A12~A11,
CKE(n-1) CKE(n) ^{CS RAS CAS WE DM BA0,1 A10/AP} _A9~A0 ^Note
H
H
LL
L LX
BA0=0; OP CODE
1,2
H
H
LL
L LX
BA1=1; OP CODE
H
H
LL
L HX
L
X
10,12
LH
HH
L
H
X
HX
XX
X
6,9,
12
Bank Active
H
Read
Auto Precharge Disable
H
Auto Precharge Enable
Write
Auto Precharge Disable
H
Auto Precharge Enable
Bank Selection
Precharge
H
All Banks
H
LL
H HX
V
H
LH
L HX
V
H
LH
L LX
V
V
H
LL
H LX
X
Row Address
L
Column
Address 1,3
H _(A9~A0)
L
Column
Address 1,3
H
(A9~A0)
L
X
H
Active Power-Down
Entry
Exit
HX
XX
H
L
X
LH
HH
HX
XX
L
H
X
LH
HH
4,11,
12,15
X
4,8,
12,15
Precharge Power-Down
Entry
Exit
HX
XX
H
L
X
LH
HH
HX
XX
L
H
X
LH
HH
4,11,
12,15
X
4,8,
12,15
DM
H
H
X
V
X
16
Device Deselect
H
X
HX
X XX
X
No Operation
H
X
LH
H HX
X
(OP code = Operand Code, V = Valid, X = Don’t Care, H = Logic High, L = Logic Low)
Note:
1. BA during a MRS/EMRS command selects which mode register is programmed.
2. MRS/EMRS can be issued only at all bank Precharge state.
3. Burst Reads or Writes at BL = 4 cannot be terminated or interrupted.
4. The Power-Down mode does not perform any Refresh operations. The duration of Power-Down is limited by the Refresh
requirements. Need one clock delay to entry and exit mode.
5. The state of ODT does not affect the states described in this table. The ODT function is not available during Self Refresh.
6. Self Refresh Exit is asynchronous.
7. CKE (n) is the logic state of CKE at clock edge n; CKE (n–1) was the state of CKE at the previous clock edge.
8. All states not shown are illegal or reserved unless explicitly described elsewhere in this document.
9. On Self Refresh, Exit Deselect or NOP commands must be issued on every clock edge occurring during the t_XSNR period.
Read commands may be issued only after tXSRD is satisfied.
10. Self Refresh mode can only be entered from all banks Idle state.
11. Power-Down and Self Refresh can not be entered while Read or Write operations, MRS/EMRS operations or Precharge
operations are in progress.
12. Minimum CKE HIGH / LOW time is t_CKE (min).
13. The state of ODT does not affect the states described in this table. The ODT function is not available during Self Refresh.
14. CKE must be maintained HIGH while the device is in OCD calibration mode.
15. ODT must be driven HIGH or LOW in Power-Down if the ODT function is enabled.
16. Used to mask write data, provided coincident with the corresponding data.
Elite Semiconductor Memory Technology Inc.
Publication Date : Feb. 2009
Revision : 1.1
21/59