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M14D5121632A_1 Datasheet, PDF (13/59 Pages) Elite Semiconductor Memory Technology Inc. – 8M x 16 Bit x 4 Banks DDR II SDRAM
ESMT
M14D5121632A
Operation Temperature Condition (TC) -40°C~95°C
Parameter
Symbol
-3
Min.
Max.
Unit Note
Minimum time clocks remains
ON after CKE asynchronously
tDELAY tIS + tCK (avg)+tIH
-
ns
drops low
Output impedance test driver
delay
tOIT
0
12
ns
MRS command to ODT update
delay
tMOD
0
12
ns
ODT turn-on delay
ODT turn-on
ODT turn-on (Power-Down
mode)
ODT turn-off delay
ODT turn-off
ODT turn-off (Power-Down
mode)
ODT to Power-Down entry
latency
tAOND
2
2
tCK
tAON
tAC(min.)
tAC(max.) +
700
ps
14,16
2 x tCK
tAONPD tAC(min.) + 2000 +tAC(max.) +
ps
1000
tAOFD
2.5
2.5
tCK
15,17
,18
tAOF
tAC(min.)
tAC(max.) +
600
ps
2.5 x tCK
tAOFPD tAC(min.) + 2000 +tAC(max.) +
ps
1000
tANPD
3
3
tCK
ODT Power-Down exit latency
tAXPD
8
8
tCK
Note:
1. For each of the terms above, if not already an integer, round to the next higher integer.
2. AL: Additive Latency.
3. MRS A12 bit defines which Active Power-Down Exit timing to be applied.
4. The figures of Input Waveform Timing 1 and 2 are referenced from the input signal crossing at the VIH (AC) level for a rising
signal and VIL (AC) for a falling signal applied to the device under test.
5. The figures of Input Waveform Timing 1 and 2 are referenced from the input signal crossing at the VIL (DC) level for a rising
signal and VIH (DC) for a falling signal applied to the device under test.
6. tHP is the minimum of the absolute half period of the actual input clock. tHP is an input parameter but not an input
specification parameter. It is used in conjunction with tQHS to derive the DRAM output timing tQH. The value to be used for tQH
calculation is determined by the following equation;
tHP = Min ( tCH (abs), tCL (abs) ), where:
tCH (abs) is the minimum of the actual instantaneous clock HIGH time;
tCL (abs) is the minimum of the actual instantaneous clock LOW time;
Elite Semiconductor Memory Technology Inc.
Publication Date : Feb. 2009
Revision : 1.1
13/59