M14D5121632A_1 Datasheet, PDF (39/59 Pages) Elite Semiconductor Memory Technology Inc. – 8M x 16 Bit x 4 Banks DDR II SDRAM

ESMT
M14D5121632A
Operation Temperature Condition (TC) -40°C~95°C
Burst Write followed by Burst Read
< RL= 5 (AL= 2; CL= 3); WL= 4; BL= 4 >
T0
T1
T2
T3
T4
T5
T6
T7
CLK
CLK
Write to Read = CL -1+BL/2+tWTR
CMD
NOP
NOP
NOP
NOP
Posted CAS
READ A
NOP
NOP
NOP
DQS,DQS
DQS
DQS
WL = RL -1 = 4
DQ
DinA0 DinA1 DinA2 DinA3
AL = 2
> = tWTR
CL = 3
RL = 5
T8
NOP
T9
NOP
DoutA0
Note: The minimum number of clock from the Burst Write command to the Burst Read command is [CL - 1 + BL/2
+ t_WTR]. This t_WTR is not a write recovery time (WR) but the time required to transfer the 4 bit write data from
the input buffer into sense amplifiers in the array.
Seamless Burst Write
CLK
CLK
CMD
< RL= 5; WL= 4; BL= 4 >
T0
T1
T2
T3
T4
T5
T6
T7
T8
Posted CAS
WRITE A
NOP
Posted CAS
WRITE B
NOP
NOP
NOP
NOP
NOP
NOP
DQS,DQS
DQs
WL = RL-1 = 4
DinA0 DinA1 DinA2 DinA3 DinB0 DinB1 DinB2 DinB3
Note: The seamless burst write operation is supported by enabling a Write command at every other clock for BL =
4 operation, and every 4 clock for BL = 8 operation. This operation is allowed regardless of same or different
banks as long as the banks are activated.
Elite Semiconductor Memory Technology Inc.
Publication Date : Feb. 2009
Revision : 1.1
39/59