M14D5121632A_1 Datasheet, PDF (1/59 Pages) Elite Semiconductor Memory Technology Inc. – 8M x 16 Bit x 4 Banks DDR II SDRAM

ESMT
M14D5121632A
Operation Temperature Condition (TC) -40°C~95°C
DDR II SDRAM
8M x 16 Bit x 4 Banks
DDR II SDRAM
Features
z JEDEC Standard
z V_DD = 1.8V ± 0.1V, V_DDQ = 1.8V ± 0.1V
z Internal pipelined double-data-rate architecture; two data access per clock cycle
z Bi-directional differential data strobe (DQS, /DQS); /DQS can be disabled for single-ended data strobe operation.
z On-chip DLL
z Differential clock inputs (CLK and CLK )
z DLL aligns DQ and DQS transition with CLK transition
z Quad bank operation
z CAS Latency : 3, 4, 5
z Additive Latency: 0, 1, 2, 3, 4
z Burst Type : Sequential and Interleave
z Burst Length : 4, 8
z All inputs except data & DM are sampled at the rising edge of the system clock(CLK)
z Data I/O transitions on both edges of data strobe (DQS)
z DQS is edge-aligned with data for READ; center-aligned with data for WRITE
z Data mask (DM) for write masking only
z Off-Chip-Driver (OCD) impedance adjustment
z On-Die-Termination for better signal quality
z Special function support
- 50/ 75/ 150 ohm ODT
- High Temperature Self refresh rate enable
z Auto & Self refresh
z Refresh cycle :
- 8192 cycles/64ms (7.8μs refresh interval) at -40 ℃ ≦ T_C ≦ +85 ℃
- 8192 cycles/32ms (3.9μs refresh interval) at +85 ℃ ＜ T_C ≦ +95 ℃
z SSTL_18 interface
z 84-ball BGA package
Ordering Information:
PRODUCT NO.
MAX FREQ
VDD
Data rate
(CL-tRCD-tRP)
PACKAGE COMMENTS
M14D5121632A -3BIG
333MHz
1.8V
DDR2-667 (5-5-5)
BGA
Pb-free
Elite Semiconductor Memory Technology Inc.
Publication Date : Feb. 2009
Revision : 1.1
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