M14D5121632A_1 Datasheet, PDF (26/59 Pages) Elite Semiconductor Memory Technology Inc. – 8M x 16 Bit x 4 Banks DDR II SDRAM

ESMT
M14D5121632A
Operation Temperature Condition (TC) -40°C~95°C
Extended Mode Register Set-2 [EMRS(2)]
The EMRS(2) stores the data for enabling or disabling high temperature self refresh rate. The default value of the EMRS(2) is not
defined, therefore EMRS(2) must be written after power up for proper operation. The EMRS(2) is written by asserting LOW on CS ,
RAS , CAS , WE , BA0 and HIGH on BA1 (The device should be in all bank Precharge with CKE already high prior to writing into
EMRS(2)). The state of address pins A0~A12 in the same cycle as CS , RAS , CAS , WE and BA0 going LOW and BA1 going
HIGH are written in the EMRS(2).
The t_MRD time is required to complete the write operation to the EMRS(2). The EMRS(2) contents can be changed using the same
command and clock cycle requirements during normal operation as long as all banks are in the idle state. A7 is used for high
temperature self refresh rate enable or disable.
BA1 BA0
A12
A11 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0
10
0
SRF
0
BA1 BA0 Mode Register
0 0 MRS
0 1 EMRS(1)
1 0 EMRS(2)
1 1 EMRS(3): Reserve
A7 ^{High Temperature}
Self Refresh rate
0
Disable
1
Enable
Note: All bits except A7, BA0 and BA1 are reserved for future use and must be set to 0.
Extended Mode Register Set-3 [EMRS(3)]
BA1 BA0
A12
A11 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0
11
0
BA1 BA0 Mode Register
0 0 MRS
0 1 EMRS(1)
1 0 EMRS(2)
1 1 EMRS(3): Reserve
Note: EMRS(3) is reserved for future. All bits except BA0 and BA1 are reserved for future use and must be set to 0 when
setting to mode register during initialization.
Elite Semiconductor Memory Technology Inc.
Publication Date : Feb. 2009
Revision : 1.1
26/59