M14D5121632A_1 Datasheet, PDF (36/59 Pages) Elite Semiconductor Memory Technology Inc. – 8M x 16 Bit x 4 Banks DDR II SDRAM

ESMT
M14D5121632A
Operation Temperature Condition (TC) -40°C~95°C
Essential Functionality for DDR2 SDRAM
Burst Read Operation
The Burst Read command is initiated by having CS and CAS LOW while holding RAS and WE HIGH at the rising edge of
the clock. The address inputs determine the starting column address for the burst. The delay from the start of the command to
when the data from the first cell appears on the outputs is equal to the value of the read latency (RL). The DQS is driven LOW 1
clock cycle before valid data (DQ) is driven onto the data bus. The first bit of the burst is synchronized with the rising edge of DQS.
Each subsequent data-out appears on the DQ pin in phase with the DQS signal in a source synchronous manner.
The RL is equal to an additive latency (AL) plus CAS latency (CL). The CL is defined by the MRS and the AL is defined by the
EMRS(1).
Read (Data Output) Timing
CLK
CLK
DQS
DQS
DQ
tCH
tCL
tRPRE
Dout0
tDQSQ(max.)
tQH
tRPST
Dout1 Dout2 _Dout3
tDQSQ(max.)
tQH
CLK
CLK
CMD
T0
T1
Posted CAS
READ A
NOP
DQS,DQS
AL = 2
DQs
Burst Read
< RL= 5 (AL= 2; CL= 3); BL= 4 >
T2
T3
T4
T5
T6
T7
T8
NOP
NOP
NOP
CL = 3
RL = 5
NOP
NOP
=< tDQSCK
NOP
DoutA0 DoutA1 DoutA2 DoutA3
NOP
< RL= 3 (AL= 0; CL= 3); BL= 8 >
T0
T1
T2
T3
T4
T5
T6
T7
T8
CLK
CLK
CMD
READ A
NOP
NOP
DQS,DQS
DQs
CL = 3
RL = 3
NOP
NOP
=< tDQSCK
NOP
NOP
NOP
DoutA0 DoutA1 DoutA2 DoutA3 DoutA4 DoutA5 DoutA6 DoutA7
NOP
Elite Semiconductor Memory Technology Inc.
Publication Date : Feb. 2009
Revision : 1.1
36/59