M14D5121632A_1 Datasheet, PDF (55/59 Pages) Elite Semiconductor Memory Technology Inc. – 8M x 16 Bit x 4 Banks DDR II SDRAM

ESMT
M14D5121632A
Operation Temperature Condition (TC) -40°C~95°C
Current State _{CS RAS CAS WE}
Address
Command
Action
H X X XX
L H H HX
L H L H BA, CA, A10
DESEL
NOP
READ / READA
NOP (Bank Active after t_WR)
NOP (Bank Active after t_WR)
ILLEGAL (*1, 6)
WRITE
L
H
L
L BA, CA, A10
RECOVERING _L
L
H
H BA, RA
WRITE / WRITEA
Active
WRITE / WRITEA
ILLEGAL (*1)
L
L
H
L BA, A10 / A10
PRE / PREA
ILLEGAL (*1) / ILLEGAL
L
L
L
HX
Refresh
ILLEGAL
L
L
L
L Op-Code Mode-Add MRS / EMRS
ILLEGAL
H X X XX
L H H HX
WRITE
RECOVERING ^L
H
L
X BA, CA, A10
with
AUTO
L
L
H
H BA, RA
PRECHARGE L
L
H
L BA, A10 / A10
L
L
L
HX
DESEL
NOP (Bank Active after t_WR)
NOP
NOP (Bank Active after t_WR)
READ / READA /
WRITE / WRITEA
ILLEGAL (*1)
Active
ILLEGAL (*1)
PRE / PREA
ILLEGAL (*1) / ILLEGAL
Refresh
ILLEGAL
L
L
L
L Op-Code Mode-Add MRS / EMRS
ILLEGAL
REFRESH
H X X XX
L H H HX
L H L X BA, CA, A10
L
L
H
H BA, RA
DESEL
NOP (Idle after t_RFC)
NOP
NOP (Idle after t_RFC)
READ / READA /
WRITE / WRITEA
ILLEGAL
Active
ILLEGAL
L
L
H
L BA, A10 / A10
PRE / PREA
ILLEGAL
L
L
L
HX
Refresh
ILLEGAL
L
L
L
L Op-Code Mode-Add MRS / EMRS
ILLEGAL
H X X XX
L H H HX
(Extended)
L H L X BA, CA, A10
MODE
REGISTER
L
L
H H BA, RA
SETTING
L
L
H
L BA, A10 / A10
DESEL
NOP (Idle after t_MRD)
NOP
NOP (Idle after t_MRD)
READ / READA /
WRITE / WRITEA
ILLEGAL
Active
ILLEGAL
PRE / PREA
ILLEGAL
L
L
L
HX
Refresh
ILLEGAL
L
L
L
L Op-Code Mode-Add MRS / EMRS
H = High Level, L = Low level, X = Don’t Care
BA = Bank Address, RA =Row Address, CA = Column Address, NOP = No Operation
ILLEGAL = Device operation and / or data integrity are not guaranteed.
ILLEGAL
Note :
1. This command may be issued for other banks, depending on the state of the banks.
2. All banks must be in “IDLE”.
3. All AC timing specs must be met.
4. Only allowed at the boundary of 4 bits burst. Burst interruption at other timings is illegal.
5. Available in case t_RCD is satisfied by AL setting.
6. Available in case t_WTR is satisfied.
Elite Semiconductor Memory Technology Inc.
Publication Date : Feb. 2009
Revision : 1.1
55/59