M14D5121632A_1 Datasheet, PDF (17/59 Pages) Elite Semiconductor Memory Technology Inc. – 8M x 16 Bit x 4 Banks DDR II SDRAM

ESMT
M14D5121632A
Operation Temperature Condition (TC) -40°C~95°C
6. t_JIT (cc) is defined as the difference in clock period between two consecutive clock cycles : t_JIT (cc) = Max. of | t_CK i +1 - t_CK i|
t_JIT (cc) defines the cycle to cycle jitter when the DLL is already locked.
t_JIT (cc, lck) uses the same definition for cycle to cycle jitter, during the DLL locking period only.
t_JIT (cc) and t_JIT (cc, lck) are not subject to production testing.
7. t_ERR (nper) is defined as the cumulative error across multiple consecutive cycles from t_CK (avg).
t_ERR (nper) is not subject to production testing.
8. These parameters are specified per their average values, however it is understood that the following relationship between
the average timing and the absolute instantaneous timing holds at all times. (Min. and max. of SPEC values are to be used
for calculations in the table below.)
Parameter
Symbol
Min.
Max.
Absolute clock period
t_CK (abs) t_CK (avg)(min.) + t_JIT (per)(min.)
Absolute clock high pulse width
t_CH (abs)
t_CH (avg)(min.) x t_CK (avg)(min.) +
t_JIT (duty)(min.)
Absolute clock low pulse width
t_CL (abs)
t_CL (avg)(min.) x t_CK (avg)(min.) +
t_JIT (duty)(min.)
Example: For DDR2-667, t_CH (abs)(min.) = (0.48 x 3000ps) – 125 ps = 1315 ps
t_CK (avg)(max.) + t_JIT (per)(max.)
t_CH (avg)(max.) x t_CK (avg)(max.)
+ t_JIT (duty)(max.)
t_CL (avg)(max.) x t_CK (avg)(max.)
+ t_JIT (duty)(max.)
Unit
ps
ps
ps
Input Slew Rate De-rating
For all input signals the total t_IS, t_DS (setup time) and t_IH, t_DH (hold time) required is calculated by adding the data sheet t_IS (base), t_DS
(base) and t_IH (base), t_DH (base) value to the Δt_IS, Δt_DS and Δt_IH, Δt_DH de-rating value respectively.
Example: t_DS (total setup time) = t_DS (base) + Δt_DS.
Setup (t_IS, t_DS) nominal slew rate for a rising signal is defined as the slew rate between the last crossing of V_REF (DC) and the first
crossing of V_IH (AC)(min.). Setup (t_IS, t_DS) nominal slew rate for a falling signal is defined as the slew rate between the last crossing
of V_REF (DC) and the first crossing of V_IL (AC)(max.). If the actual signal is always earlier than the nominal slew rate line between
shaded ‘V_REF (DC) to AC region’, use nominal slew rate for de-rating value (See the figure of Slew Rate Definition Nominal).
If the actual signal is later than the nominal slew rate line anywhere between shaded ‘V_REF (DC) to AC region’, the slew rate of a
tangent line to the actual signal from the AC level to DC level is used for de-rating value (see the figure of Slew Rate Definition
Tangent).
Hold (t_IH, t_DH) nominal slew rate for a rising signal is defined as the slew rate between the last crossing of V_IL (DC)(max.) and the
first crossing of V_REF (DC). Hold (t_IH, t_DH) nominal slew rate for a falling signal is defined as the slew rate between the last crossing
of V_IH (DC)(min.) and the first crossing of V_REF (DC). If the actual signal is always later than the nominal slew rate line between
shaded ‘DC level to V_REF (DC) region’, use nominal slew rate for de-rating value (See the figure of Slew Rate Definition Nominal).
If the actual signal is earlier than the nominal slew rate line anywhere between shaded ‘DC to V_REF (DC) region’, the slew rate of a
tangent line to the actual signal from the DC level to V_REF (DC) level is used for de-rating value (see the figure of Slew Rate
Definition Tangent).
Although for slow slew rates the total setup time might be negative (i.e. a valid input signal will not have reached V_IH / V_IL (AC) at
the time of the rising clock transition) a valid input signal is still required to complete the transition and reach V_IH / V_IL (AC).
For slew rates in between the values listed in the tables below, the de-rating values may be obtained by linear interpolation. These
values are typically not subject to production test. They are verified by design and characterization.
Elite Semiconductor Memory Technology Inc.
Publication Date : Feb. 2009
Revision : 1.1
17/59