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M14D5121632A_1 Datasheet, PDF (16/59 Pages) Elite Semiconductor Memory Technology Inc. – 8M x 16 Bit x 4 Banks DDR II SDRAM
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ESMT
M14D5121632A
Operation Temperature Condition (TC) -40°C~95°C
Clock Jitter [ DDR2- 667 ]
Parameter
Symbol
-3
Min.
Max.
Unit Note
Average clock period
Clock period jitter
Clock period jitter during
DLL locking period
tCK (avg)
tJIT (per)
tJIT (per,lck)
3000
-125
-100
8000
125
100
ps 1
ps 5
ps 5
Cycle to cycle period jitter
Cycle to cycle clock period jitter
During DLL locking period
tJIT (cc)
tJIT (cc, lck)
-
250
ps 6
-
200
ps 6
Cumulative error across 2 cycles
tERR (2per)
-175
175
Cumulative error across 3 cycles
tERR (3per)
-225
225
Cumulative error across 4 cycles
tERR (4per)
-250
250
Cumulative error across 5 cycles
tERR (5per)
-250
250
Cumulative error across
n=6,7,8,9,10 cycles
tERR (6-10per)
-350
350
ps 7
ps 7
ps 7
ps 7
ps 7
Cumulative error across
n=11,12,….49,50 cycles
tERR (11-50per)
-450
450
ps 7
Average high pulse width
tCH (avg)
0.48
0.52
tCK (avg) 2
Average low pulse width
tCL (avg)
0.48
0.52
tCK (avg) 3
Duty cycle jitter
tJIT (duty)
-125
125
ps 4
Note:
1. tCK (avg) is calculated as the average clock period across any consecutive 200 cycle window.
2. tCH (avg) is defined as the average HIGH pulse width, as calculated across any consecutive 200 HIGH pulses.
3. tCL (avg) is defined as the average LOW pulse width, as calculated across any consecutive 200 LOW pulses.
4. tJIT (duty) is defined as the cumulative set of tCH jitter and tCL jitter. tCH jitter is the largest deviation of any single tCH from tCH
(avg). tCL jitter is the largest deviation of any single tCL from tCL (avg).
tJIT (duty) is not subject to production test.
tJIT (duty) = Min./Max. of { tJIT (CH), tJIT (CL)}, where:
tJIT (CH) = { tCH j - tCH (avg) where j =1 to 200}
tJIT (CL) = {tCL j - tCL (avg) where j =1 to 200}
5. tJIT (per) is defined as the largest deviation of any single tCK from tCK (avg).
tJIT (per) = Min./Max. of { tCK j - tCK (avg) where j =1 to 200}
tJIT (per) defines the single period jitter when the DLL is already locked.
tJIT (per, lck) uses the same definition for single period jitter, during the DLL locking period only.
tJIT (per) and tJIT (per, lck) are not subject to production testing.
Elite Semiconductor Memory Technology Inc.
Publication Date : Feb. 2009
Revision : 1.1
16/59
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