M14D2561616A-2E Datasheet, PDF (7/61 Pages) Elite Semiconductor Memory Technology Inc. – Internal pipelined double-data-rate architecture; two data access per clock cycle

ESMT
M14D2561616A (2E)
Automotive Grade
Parameter
Symbol
Test Condition
Version
Unit
-1.8
-2.5
t_CK = t_CK (IDD);
Refresh command every t_RFC (IDD) interval;
Burst Refresh Current IDD5 CKE is HIGH, CS is HIGH between valid commands; 75
65 mA
Other control and address bus inputs are SWITCHING;
Data bus inputs are SWITCHING
Self Refresh Mode;
Self Refresh Current IDD6 ^{CLK and CLK at 0V; CKE ≤ 0.2V;}
6
Other control and address bus inputs are FLOATING;
6 mA
Data bus inputs are FLOATING
Operating Current
(Bank interleaving)
All bank interleaving Reads, I_OUT = 0mA;
BL = 4, CL= CL (IDD), AL = t_RCD (IDD) – 1 × t_CK (IDD);
t_CK = t_CK (IDD), t_RC = t_RC (IDD),
IDD7 t_RRD = t_RRD (IDD), t_RCD = 1 × t_CK (IDD);
155
CKE is HIGH, CS is HIGH between valid commands;
135 mA
Address bus inputs are STABLE during Deslects;
Data pattern is the same as IDD4W;
Note:
1. IDD specifications are tested after the device is properly initialized.
2. Input slew rate is specified by AC Input Test Condition.
3. IDD parameters are specified with ODT disabled.
4. Data bus consists of DQ, DM, DQS and DQS , IDD values must be met with all combinations of EMRS bits 10 and 11.
5. Definitions for IDD:
LOW is defined as V_IN ≤ V_IL (AC) (max.).
HIGH is defined as V_IN ≥ V_IH (AC) (min.).
STABLE is defined as inputs stable at a HIGH or LOW level.
FLOATING is defined as inputs at V_REF = V_DDQ/2
SWITCHING is defined as:
Address and control signal Inputs are changed between HIGH and LOW every other clock cycle (once per two clocks),
and DQ (not including mask or strobe) signal inputs are changed between HIGH and LOW every other data transfer
(once per clock).
6. The following IDD values must be derated (IDD limits increase), when T_C ≧ +85 ℃. IDD2P must derated by 20%; IDD3P (slow)
must derated by 30% and IDD6 must be derated by 80%. (IDD6 will increase by this amount if T_C ≧ +85 ℃ and double refresh
option is still enabled.)
7. AC Timing for IDD test conditions
For purposes of IDD testing, the following parameters are to be utilized.
Parameter
-1.8
DDR2-1066 (7-7-7)
-2.5
Unit
DDR2-800 (5-5-5)
CL (IDD)
tRCD (IDD)
7
13.125
5
t_CK
12.5
ns
tRC (IDD)
58.125
57.5
ns
tRRD (IDD)-1KB
7.5
7.5
ns
tCK (IDD)
1.875
2.5
ns
tRAS (IDD) min.
45
45
ns
tRAS (IDD) max.
70000
ns
tRP (IDD)
13.125
12.5
ns
tRFC (IDD)
75
75
ns
Elite Semiconductor Memory Technology Inc.
Publication Date : Jun. 2014
Revision : 1.0
7/61