M14D2561616A-2E Datasheet, PDF (11/61 Pages) Elite Semiconductor Memory Technology Inc. – Internal pipelined double-data-rate architecture; two data access per clock cycle

ESMT
AC Timing Parameter & Specifications
Parameter
Symbol
-1.8
Min.
Max.
CL=7
1875
7500
Clock period
CL=6
CL=5
CL=4
DQ output access time from
CLK/ CLK
t_CK (avg)
t_AC
2500
3000
3750
-350
7500
7500
7500
+350
CLK high-level width
CLK low-level width
DQS output access time from
CLK/ CLK
t_CH (avg)
t_CL (avg)
t_DQSCK
0.48
0.48
-325
0.52
0.52
+325
Clock to first rising edge of DQS
delay
t_DQSS
-0.25
+0.25
Data-in and DM setup time
(to DQS)
t_DS
(base)
0
Data-in and DM hold time
(to DQS)
t_DH
(base)
75
DQ and DM input pulse width
(for each input)
t_DIPW
0.35
Address and Control Input
setup time
t_IS (base)
125
Address and Control Input hold
time
t_IH (base)
200
Control and Address input pulse
width
t_IPW
0.6
DQS input high pulse width
DQS input low pulse width
DQS falling edge to CLK rising
setup time
t_DQSH
t_DQSL
t_DSS
0.35
0.35
0.2
DQS falling edge from CLK
rising hold time
t_DSH
0.2
Data strobe edge to output data
edge
t_DQSQ
175
Data-out high-impedance
window from CLK/ CLK
t_HZ
t_AC(max.)
Data-out low-impedance window tLZ
from CLK/ CLK
(DQS)
t_AC(min.)
t_AC(max.)
DQ low-impedance window from tLZ
CLK/ CLK
(DQ)
2 x t_AC(min.)
t_AC(max.)
Half clock period
t_HP
DQ/DQS output hold time from
DQS
t_QH
Min (t_CL, t_CH)
t_HP-t_QHS
Elite Semiconductor Memory Technology Inc.
M14D2561616A (2E)
Automotive Grade
-2.5
Min.
Max.
-
-
-
-
2500
8000
3750
8000
-400
+400
0.48
0.52
0.48
0.52
-350
+350
Unit Note
ps
12
ps
9
t_CK (avg) 12
t_CK (avg) 12
ps
9
-0.25
50
125
0.35
175
250
0.6
0.35
0.35
0.2
0.2
+0.25
200
t_CK (avg)
ps
3
ps
4
t_CK (avg)
ps
3
ps
4
t_CK (avg)
t_CK (avg)
t_CK (avg)
t_CK (avg)
t_CK (avg)
ps
t_AC(max.)
ps
9
t_AC(min.)
t_AC(max.)
ps
9
2 x t_AC(min.)
Min (t_CL, t_CH)
t_HP-t_QHS
t_AC(max.)
ps
9
ps 5,12
ps
Publication Date : Jun. 2014
Revision : 1.0
11/61