M14D2561616A-2E Datasheet, PDF (36/61 Pages) Elite Semiconductor Memory Technology Inc. – Internal pipelined double-data-rate architecture; two data access per clock cycle

ESMT
M14D2561616A (2E)
Automotive Grade
Precharge
The Precharge command is used to precharge or close a bank that has activated. The command is issued when CS , RAS
and WE are LOW and CAS is HIGH at the rising edge of the clock. The Precharge command can be used to precharge
each bank respectively or all banks simultaneously. The bank select addresses (BA0, BA1) and A10 are used to define which
bank is precharged when the command is initiated. For write cycle, t_WR(min.) must be satisfied until the Precharge command
can be issued. After t_RP from the precharge, a Bank Active command to the same bank can be initiated.
A10/AP
Bank Selection for Precharge by Address bits
BA1
BA0
Precharge
0
0
0
0
1
0
0
0
1
0
1
1
1
X
X
Bank A Only
Bank B Only
Bank C Only
Bank D Only
All Banks
NOP & Device Deselect
The device should be deselected by deactivating the CS signal. In this mode, DDR2 SDRAM would ignore all the control
inputs. The DDR2 SDRAM are put in NOP mode when CS is active and by deactivating RAS , CAS and WE . For both
Deselect and NOP, the device should finish the current operation when this command is issued.
Bank Active
The Bank Active command is issued by holding CAS and WE HIGH with CS and RAS LOW at the rising edge of the
clock (CLK). The DDR2 SDRAM has four independent banks, so two Bank Select addresses (BA0, BA1) are required. The Bank
Active command to the first Read or Write command must meet or exceed the minimum of RAS to CAS delay time
(t_RCD(min.)). Once a bank has been activated, it must be precharged before another Bank Active command can be applied to the
same bank. The minimum time interval between interleaved Bank Active command (Bank A to Bank B and vice versa) is the
Bank to Bank delay time (t_RRD min).
Bank Active Command Cycle
T0
T1
T2
T3
Tn
Tn+1
Tn+2
Tn+3
CLK
CLK
Command
ACT
Posted
READ
ACT
Posted
READ
PRE
PRE
ACT
Address
Bank A
Row Addr.
Bank A
Col. Addr.
Bank B
Row Addr.
Bank B
Col. Addr.
Bank A
tRCD=1
tCCD
Additive latency (AL)
Bank A Read begins
tRRD
tRAS
tRC
Bank A
Active
Bank B
Active
Bank A
Precharge
Bank B
Bank A
Row Addr.
tRP
Bank B Bank A
Precharge Active
Elite Semiconductor Memory Technology Inc.
Publication Date : Jun. 2014
Revision : 1.0
36/61