M14D2561616A-2E Datasheet, PDF (6/61 Pages) Elite Semiconductor Memory Technology Inc. – Internal pipelined double-data-rate architecture; two data access per clock cycle

ESMT
M14D2561616A (2E)
Automotive Grade
DC Specifications
(IDD values are for the operation range of Voltage and Temperature)
Parameter
Symbol
Test Condition
Operating Current
(Active - Precharge)
IDD0
Operating Current
(Active - Read -
Precharge)
IDD1
One bank;
t_CK = t_CK (IDD), t_RC = t_RC (IDD), t_RAS = t_RAS (IDD)min;
CKE is High, CS is HIGH between valid commands;
Address bus inputs are SWITCHING;
Data bus inputs are SWITCHING
One bank; I_OUT = 0mA;
BL = 4, CL = CL(IDD), AL = 0;
t_CK = t_CK (IDD), t_RC = t_RC (IDD),
t_RAS = t_RAS (IDD)min, t_RCD = t_RCD (IDD);
CKE is HIGH, CS is HIGH between valid commands;
Address bus inputs are SWITCHING;
Data pattern is same as IDD4W
Precharge
Power-Down
Standby Current
IDD2P
All banks idle;
t_CK = t_CK (IDD); CKE is LOW;
Other control and address bus inputs are STABLE;
Data bus inputs are FLOATING
Precharge Quiet
Standby Current
IDD2Q
All banks idle;
t_CK = t_CK (IDD); CKE is HIGH, CS is HIGH;
Other control and address bus inputs are STABLE;
Data bus inputs are FLOATING
Idle Standby Current IDD2N
All banks idle;
t_CK = t_CK (IDD); CKE is HIGH, CS is HIGH;
Other control and address bus inputs are SWITCHING;
Data bus inputs are SWITCHING
Active Power-down
Standby Current
IDD3P
All banks open;
t_CK = t_CK (IDD); CKE is LOW;
Other control and address bus inputs
are STABLE;
Data bus input are FLOATING
Fast PDN Exit
MRS(12) = 0
Slow PDN Exit
MRS(12) = 1
Active Standby
Current
Operation Current
(Read)
Operation Current
(Write)
IDD3N
All banks open;
t_CK = t_CK (IDD), t_RAS = t_RAS (IDD)max, t_RP = t_RP (IDD);
CKE is HIGH, CS is HIGH between valid commands;
Other control and address bus inputs are SWITCHING;
Data bus inputs are SWITCHING
IDD4R
All banks open, continuous burst Reads, I_OUT = 0mA;
BL = 4, CL = CL (IDD), AL = 0;
t_CK = t_CK (IDD), t_RAS = t_RAS (IDD)max, t_RP = t_RP (IDD);
CKE is HIGH, CS is HIGH between valid commands;
Address bus inputs are SWITCHING;
Data pattern is the same as IDD4W;
IDD4W
All banks open, continuous burst Writes;
BL = 4, CL = CL (IDD), AL = 0;
t_CK = t_CK (IDD), t_RAS = t_RAS (IDD)max, t_RP = t_RP (IDD);
CKE is HIGH, CS is HIGH between valid commands;
Address bus inputs are SWITCHING;
Data bus inputs are SWITCHING
Version
Unit
-1.8
-2.5
65
60 mA
85
75 mA
12
10 mA
40
35 mA
35
30 mA
50
45
mA
15
15
45
40 mA
140
130 mA
120
110 mA
Elite Semiconductor Memory Technology Inc.
Publication Date : Jun. 2014
Revision : 1.0
6/61