M14D2561616A-2E Datasheet, PDF (16/61 Pages) Elite Semiconductor Memory Technology Inc. – Internal pipelined double-data-rate architecture; two data access per clock cycle

ESMT
M14D2561616A (2E)
Automotive Grade
ODT DC Electrical Characteristics
Parameter
Rtt effective impedance value for 75Ω setting
EMRS(1) [A6, A2] = 0, 1
Rtt effective impedance value for 150Ω setting
EMRS(1) [A6, A2) = 1, 0
Rtt effective impedance value for 50Ω setting
EMRS(1) [A6, A2] = 1, 1
Deviation of VM with respect to V_DDQ /2
Symbol
Rtt1(eff)
Rtt2(eff)
Rtt3(eff)
△VM
Min.
60
120
40
-6
Typ.
75
150
50
-
Max.
Unit
90
Ω
180
Ω
60
Ω
+6
%
Note:
Measurement Definition for Rtt(eff) :
Rtt(eff) is determined by separately applying VIH(AC) and VIL(AC) to test pin, and then measuring current I(VIH(AC)) and
I(VIL(AC)) respectively.
Measurement Definition for △VM :
Measure voltage (VM) at test pin with no load.
OCD Default Characteristics
Parameter
Output impedance
Output impedance step size for
OCD calibration
Pull-up and pull-down mismatch
Min.
12.6
0
0
Typ.
18
-
-
Max.
23.4
1.5
4
Unit
Note
Ω
1
Ω
6
Ω
1,2,3
Output slew rate
1.5
-
5
V/ns 1,4,5,7,8
Note:
1. Absolute specifications: the operation range of Voltage and Temperature.
2. Impedance measurement condition for output source DC current: VDDQ = 1.7V; VOUT = 1,420mV; (VOUT - VDDQ)/IOH must
be less than 23.4Ω for values of VOUT between VDDQ and VDDQ - 280mV. Impedance measurement condition for output
sink DC current: VDDQ = 1.7V; VOUT = 280mV; VOUT/IOL must be less than 23.4Ω for values of VOUT between 0V and
280mV.
3. Mismatch is absolute value between pull-up and pull-down; both are measured at same temperature and voltage.
4. Slew rate measured from VIL (AC) to VIH (AC).
5. The absolute value of the slew rate as measured from DC to DC is equal to or greater than the slew rate as measured
from AC to AC.
6. This represents the step size when the OCD is near 18 Ω at nominal conditions across all process corners/variations and
represents only the DRAM uncertainty. A 0 Ω value (no calibration) can only be achieved if the OCD impedance is 18 Ω±
0.75 Ω under nominal conditions.
7. Timing skew due to DRAM output slew rate mismatch between DQS / DQS and associated DQ’s is included in t_DQSQ
and t_QHS specification.
8. DDR2 SDRAM output slew rate test load is defined in “Output Test Load” figure of AC Operating Test Conditions.
Elite Semiconductor Memory Technology Inc.
Publication Date : Jun. 2014
Revision : 1.0
16/61