M14D2561616A-2E Datasheet, PDF (24/61 Pages) Elite Semiconductor Memory Technology Inc. – Internal pipelined double-data-rate architecture; two data access per clock cycle

ESMT
M14D2561616A (2E)
Automotive Grade
Mode Register Definition
Mode Register Set [MRS]
The mode register stores the data for controlling the various operating modes of DDR2 SDRAM. It programs CAS latency,
burst length, burst type, test mode, DLL reset, WR and various vendor specific options to make the device useful for variety of
different applications. The default value of the mode register is not defined, therefore the mode register must be written after
Power-Up for proper operation. The mode register is written by asserting LOW on CS , RAS , CAS , WE , BA0 and BA1 (The
device should be in all bank Precharge with CKE already high prior to writing into the mode register). The state of address pins
A0~A12 in the same cycle as CS , RAS , CAS , WE , BA0 and BA1 going LOW are written in the mode register.
The t_MRD time is required to complete the write operation to the mode register. The mode register contents can be changed
using the same command and clock cycle requirements during normal operation as long as all banks are in the idle state. The
mode register is divided into various fields depending on functionality. The burst length is defined by A0 ~ A2. Burst address
sequence type is defined by A3, CAS latency (read latency from column address) is defined by A4 ~ A6. The DDR2 doesn’t
support half clock latency mode. A7 is used for test mode. A8 is used for DLL reset. A7 must be set to low for normal MRS
operation. Write recovery time WR is defined by A9 ~ A11. Refer to the table for specific codes.
BA1 BA0
A12
A11 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0 Address Bus
00
PD
WR
DLL TM _{CAS Latency} BT Burst Length
Mode Register
Active Power down exit timing
A12
PD
0
Fast Exit (normal)
1 Slow Exit (low power)
A7 Mode
0
No
1
Yes
A3 Burst Type
0 Sequential
1 Interleave
BA1 BA0 Mode Register
0 0 MRS
0 1 EMRS(1)
1 0 EMRS(2)
1 1 EMRS(3) : Reserved
Write recovery for Auto Precharge
A11 A10 A9 WR(cycles)^*1
000
001
010
011
100
101
110
111
Reserved
2
3
4
5
6
7
8
A8 DLL reset
0
No
1
Yes
CAS Latency
A6 A5 A4
000
001
010
011
100
101
110
111
Latency
Reserved
Reserved
Reserved
Reserved
4
5
6
7
A2 A1 A0 Burst Length
000
001
010
011
100
101
110
111
Reserved
Reserved
4
8
Reserved
Reserved
Reserved
Reserved
Note:
1.
WR(min.) (write recovery for Auto Precharge) is determined by t_CK (max.) and WR(max.) is determined by t_CK (min.)
WR in clock cycles is calculated by dividing t_WR (in ns) by t_CK (in ns) and rounding up a non-integer value to the next
integer ( WR[cycles] = t_WR (ns)/ t_CK (ns)). The mode register must be programmed to this value. This is also used
with t_RP to determine t_DAL.
Elite Semiconductor Memory Technology Inc.
Publication Date : Jun. 2014
Revision : 1.0
24/61