M14D2561616A-2E Datasheet, PDF (1/61 Pages) Elite Semiconductor Memory Technology Inc. – Internal pipelined double-data-rate architecture; two data access per clock cycle

ESMT
DDR II SDRAM
M14D2561616A (2E)
Automotive Grade
4M x 16 Bit x 4 Banks
DDR II SDRAM
Features
z JEDEC Standard
z V_DD = 1.8V ± 0.1V, V_DDQ = 1.8V ± 0.1V
z Internal pipelined double-data-rate architecture; two data access per clock cycle
z Bi-directional differential data strobe (DQS, DQS ); DQS can be disabled for single-ended data strobe operation.
z On-chip DLL
z Differential clock inputs (CLK and CLK )
z DLL aligns DQ and DQS transition with CLK transition
z 1KB page size
- Row address: A0 to A12
- Column address: A0 to A8
z Quad bank operation
z CAS Latency : 4, 5, 6, 7
z Additive Latency: 0, 1, 2, 3, 4, 5
z Burst Type : Sequential and Interleave
z Burst Length : 4, 8
z All inputs except data & DM are sampled at the rising edge of the system clock(CLK)
z Data I/O transitions on both edges of data strobe (DQS)
z DQS is edge-aligned with data for READ; center-aligned with data for WRITE
z Data mask (DM) for write masking only
z Off-Chip-Driver (OCD) impedance adjustment
z On-Die-Termination for better signal quality
z Special function support
- 50/ 75/ 150 ohm ODT
- High Temperature Self refresh rate enable
- DCC (Duty Cycle Corrector)
z Auto & Self refresh (If T_C ＞ +95 ℃, the device can’t support Self refresh function.)
z Refresh cycle :
- 8192 cycles/64ms (7.8μ s refresh interval) at -40 ℃ ≦ T_C ≦ +85 ℃
- 8192 cycles/32ms (3.9μ s refresh interval) at +85 ℃ ＜ T_C ≦ +95 ℃
- 8192 cycles/16ms (1.95μ s refresh interval) at +95 ℃ ＜ T_C ≦ +105 ℃
z SSTL_18 interface
Elite Semiconductor Memory Technology Inc.
Publication Date : Jun. 2014
Revision : 1.0
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