M14D2561616A-2E Datasheet, PDF (13/61 Pages) Elite Semiconductor Memory Technology Inc. – Internal pipelined double-data-rate architecture; two data access per clock cycle

ESMT
M14D2561616A (2E)
Automotive Grade
AC Timing Parameter & Specifications - Continued
Parameter
CKE minimum pulse width
(high and low pulse width)
Minimum time clocks remains
ON after CKE asynchronously
drops low
Output impedance test driver
delay
MRS command to ODT update
delay
ODT turn-on delay
ODT turn-on
ODT turn-on (Power-Down
mode)
ODT turn-off delay
ODT turn-off
ODT turn-off (Power-Down
mode)
ODT to Power-Down entry
latency
ODT Power-Down exit latency
Note:
1. AL: Additive Latency.
Symbol
t_CKE
-1.8
Min.
Max.
3
-2.5
Min.
Max.
3
t_DELAY t_IS + t_CK (avg)+t_IH
t_IS + t_CK
(avg)+t_IH
t_OIT
0
12
0
12
t_MOD
t_AOND
t_AON
t_AONPD
t_AOFD
t_AOF
t_AOFPD
t_ANPD
t_AXPD
0
12
0
12
2
t_AC(min.)
t_AC(min.) + 2
2
t_AC(max.) +
2.575
2.5 x t_CK (avg)
+t_AC(max.) + 1
2
t_AC(min.)
t_AC(min.) + 2
2
t_AC(max.) + 0.7
2 x t_CK (avg)
+t_AC(max.) + 1
2.5
2.5
2.5
2.5
t_AC(min.)
t_AC(min.) + 2
t_AC(max.) + 0.6
2.5 x t_CK (avg)
+t_AC(max.) + 1
t_AC(min.)
t_AC(min.) + 2
t_AC(max.) + 0.6
2.5 x t_CK (avg)
+t_AC(max.) + 1
4
3
11
8
Unit
t_CK
ns
ns
ns
t_CK
ns
ns
t_CK
ns
ns
t_CK
t_CK
Note
13,15
14,16
,17
2. MRS A12 bit defines which Active Power-Down Exit timing to be applied.
3. The figures of Input Waveform Timing 1 and 2 are referenced from the input signal crossing at the VIH (AC) level for a
rising signal and VIL (AC) for a falling signal applied to the device under test.
4. The figures of Input Waveform Timing 1 and 2 are referenced from the input signal crossing at the VIL (DC) level for a
rising signal and VIH (DC) for a falling signal applied to the device under test.
5. t_HP is the minimum of the absolute half period of the actual input clock. t_HP is an input parameter but not an input
specification parameter. It is used in conjunction with t_QHS to derive the DRAM output timing t_QH. The value to be used for
t_QH calculation is determined by the following equation;
Elite Semiconductor Memory Technology Inc.
Publication Date : Jun. 2014
Revision : 1.0
13/61