M14D2561616A-2E Datasheet, PDF (53/61 Pages) Elite Semiconductor Memory Technology Inc. – Internal pipelined double-data-rate architecture; two data access per clock cycle

ESMT
M14D2561616A (2E)
Automotive Grade
Write with Auto Precharge to Power-Down Entry
T0
CLK
CLK
Command
T1
Tm
WRITE A
Tm+1
Tm+2
Tm+3
Tx
Tx+1
Tx+2
Tx+3
Tx+4
Tx+5
Tx+6
PRE
CKE
BL = 4
DQS
DQS
DQ
WL
DinA0 DinA1 DinA2 DinA3
tWR
T0
CLK
CLK
T1
Tm
Tm+1
Tm+2
Tm+3
Tm+4
Tm+5
Tx
Tx+1
Tx+2
Tx+3
Tx+4
Command
WRITE A
PRE
CKE
BL = 8
DQS
DQS
DQ
WL
DinA0 DinA1 DinA2 DinA3 DinA4 DinA5 DinA6 DinA7
tWR
T0
CLK
CLK
Command
CKE
Auto Refresh/ Bank Active/ Precharge to Power-Down Entry
T1
T2
T3
T4
T5
T6
T7
T8
T9
T10
T11
CMD
CKE can go to low one clock after a command
Note: CMD could be Auto Refresh/ Bank Active/ Precharge command.
MRS/EMRS to Power-Down Entry
T0 T1 T2 T3 T4 T5
CLK
CLK
Command
MRS/
EMRS
CKE
T6 T7 T8 T9 T10 T11
tMRD
Elite Semiconductor Memory Technology Inc.
Publication Date : Jun. 2014
Revision : 1.0
53/61