M14D2561616A-2E Datasheet, PDF (12/61 Pages) Elite Semiconductor Memory Technology Inc. – Internal pipelined double-data-rate architecture; two data access per clock cycle

ESMT
AC Timing Parameter & Specifications - Continued
Parameter
Symbol
DQ hold skew factor
t_QHS
Active to Precharge command
t_RAS
Active to Active command
(same bank)
t_RC
Auto Refresh row cycle time
t_RFC
Active to Read, Write delay
t_RCD
Precharge command period
t_RP
Active bank A to Active bank B
command (1KB page size)
t_RRD
Write recovery time
t_WR
Write data in to Read command
delay
t_WTR
Col. address to Col. address
delay
t_CCD
Average periodic Refresh
interval (-40℃ ≦T_C ≦ +85℃ )
t_REFI
Average periodic Refresh
interval (+85℃ ＜T_C ≦ +95℃)
t_REFI
Average periodic Refresh
interval (+95℃ ＜T_C ≦ +105℃) ^tREFI
Write preamble
Write postamble
DQS Read preamble
t_WPRE
t_WPST
t_RPRE
DQS Read postamble
t_RPST
Load Mode Register / Extended
Mode Register cycle time
t_MRD
Auto Precharge write recovery
+ Precharge time
t_DAL
Internal Read to Precharge
command delay
t_RTP
Exit Self Refresh to Read
command
t_XSRD
Exit Self Refresh to non-Read
command
t_XSNR
Exit Precharge Power-Down to
any non-Read command
t_XP
Exit Active Power-Down to
Read command
t_XARD
Exit active power-down to Read
command
(slow exit / low power mode)
t_XARDS
-1.8
Min.
45
58.125
75
13.125
13.125
7.5
15
7.5
2
0.35
0.4
0.9
0.4
2
WR + tn_RP
7.5
200
t_RFC + 10
2
2
10 - AL
Max.
250
70K
7.8
3.9
1.95
0.6
1.1
0.6
M14D2561616A (2E)
Automotive Grade
-2.5
Min.
Max.
300
45
70K
55
75
12.5
12.5
7.5
15
7.5
2
7.8
3.9
1.95
0.35
0.4
0.6
0.9
1.1
0.4
0.6
2
WR + tn_RP
7.5
200
t_RFC + 10
2
2
8 - AL
Unit Note
ps
ns
ns
ns
ns
ns
ns
ns
ns
19
t_CK
μs
μs
μs
t_CK (avg)
t_CK (avg)
t_CK (avg) 10
t_CK (avg) 11
t_CK
t_CK
18
ns
t_CK
ns
t_CK
t_CK
2
t_CK
1,2
Elite Semiconductor Memory Technology Inc.
Publication Date : Jun. 2014
Revision : 1.0
12/61