M14D2561616A-2E Datasheet, PDF (49/61 Pages) Elite Semiconductor Memory Technology Inc. – Internal pipelined double-data-rate architecture; two data access per clock cycle

ESMT
M14D2561616A (2E)
Automotive Grade
Auto Refresh & Self Refresh
Auto Refresh
An Auto Refresh command is issued by having CS , RAS and CAS held LOW with CKE and WE HIGH at the rising edge of
the clock(CLK). All banks must be precharged and idle for t_RP(min) before the Auto Refresh command is applied. An address
counter, internal to the device, supplies the bank address during the refresh cycle. No control of the external address bus is
required once this cycle has started. When the refresh cycle has completed, all banks will be in the idle state. A delay between
the Auto Refresh command and the next Bank Active command or subsequent Auto Refresh command must be greater than or
equal to the t_RFC(min).To allow for improved efficiency in scheduling and switching between tasks, some flexibility in the absolute
refresh interval is provided. A maximum of eight Refresh commands can be posted, meaning that the maximum absolute
interval between any Refresh command and the next Refresh command is 9 x t_REFI.
CLK
CLK
COMMAND
CKE = High
PRE
Au t o
Refresh
tRP
tRFC
CMD
Elite Semiconductor Memory Technology Inc.
Publication Date : Jun. 2014
Revision : 1.0
49/61