M14D2561616A-2E Datasheet, PDF(15/61 Page) Elite Semiconductor Memory Technology Inc. – Internal pipelined double-data-rate architecture; two data access per clock cycle

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M14D2561616A-2E Datasheet, PDF (15/61 Pages) Elite Semiconductor Memory Technology Inc. – Internal pipelined double-data-rate architecture; two data access per clock cycle

◁

ESMT

M14D2561616A (2E)

Automotive Grade

tAOF (max.)(derated) = tAC (max.) + 0.6 + [Max(0.5, tCH (avg)(max.)) - 0.5] x tCK (avg)

tAOF (min.)(derated) = Min(tAC (min.), tAC (min.) - [0.5 - tCH (avg)(min.)] x tCK (avg))

tAOF (max.)(derated) = 0.6 + Max(tAC (max.), tAC (max.) + [tCH (avg)(max.) - 0.5] x tCK (avg)), where:

tCH (avg)(min.) and tCH (avg)(max.) are the minimum and maximum of tCH (avg) actually measured at the DRAM input

balls.

18. tDAL [nCLK] = WR [nCLK] + tnRP [nCLK] = WR + RU {tRP [ps] / tCK (avg) [ps] }, where WR is the value programmed in the

mode register set.

19. tWTR is at lease two clocks (2 x tCK or 2 x nCK) independent of operation frequency.

Elite Semiconductor Memory Technology Inc.

Publication Date : Jun. 2014

Revision : 1.0

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