M14D2561616A-2E Datasheet, PDF (27/61 Pages) Elite Semiconductor Memory Technology Inc. – Internal pipelined double-data-rate architecture; two data access per clock cycle

ESMT
M14D2561616A (2E)
Automotive Grade
Extended Mode Register Set-2 [EMRS(2)]
The EMRS(2) controls refresh related features. The default value of the EMRS(2) is not defined, therefore EMRS(2) must be
written after power up for proper operation. The EMRS(2) is written by asserting LOW on CS , RAS , CAS , WE , BA0 and
HIGH on BA1 (The device should be in all bank Precharge with CKE already high prior to writing into EMRS(2)). The state of
address pins A0~A12 in the same cycle as CS , RAS , CAS , WE and BA0 going LOW and BA1 going HIGH are written in
the EMRS(2).
The t_MRD time is required to complete the write operation to the EMRS(2). The EMRS(2) contents can be changed using the
same command and clock cycle requirements during normal operation as long as all banks are in the idle state. A7 is used for
high temperature self refresh rate enable or disable. A3 is used for DCC enable or disable.
BA1 BA0
A12
A11 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0
10
0^*1
SRF
0^*1
DCC^*2
0^*1
BA1 BA0 Mode Register
0 0 MRS
0 1 EMRS(1)
1 0 EMRS(2)
1 1 EMRS(3): Reserved
A3
DCC Enable
0
Disable
1
Enable
A7
High Temperature
Self Refresh rate
0
Disable
1
Enable^*3
Note:
1.
2.
3.
A0~A2, A4~A6 and A8~A12 are reserved for future use and must be set to 0.
User may enable or disable the DCC (Duty Cycle Corrector) by programming A3 bit accordingly.
When DRAM is operated at 85℃＜T_C≦95℃, the extended Self Refresh rate must be enabled by setting bit A7 to “1”
before the Self Refresh mode can be entered.
Elite Semiconductor Memory Technology Inc.
Publication Date : Jun. 2014
Revision : 1.0
27/61