M14D2561616A-2E Datasheet, PDF(41/61 Page) Elite Semiconductor Memory Technology Inc. – Internal pipelined double-data-rate architecture; two data access per clock cycle

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M14D2561616A-2E Datasheet, PDF (41/61 Pages) Elite Semiconductor Memory Technology Inc. – Internal pipelined double-data-rate architecture; two data access per clock cycle

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ESMT

M14D2561616A (2E)

Automotive Grade

Burst Write followed by Burst Read

CLK

< RL= 5 (AL= 2; CL= 3); WL= 4; BL= 4 >

CLK

Write to Read = CL -1+BL/2+tWTR

CMD

NOP

Posted CAS

READ A

NOP

DQS,DQS

WL = RL -1 = 4

DQS

DinA0 DinA1 DinA2 DinA3

AL = 2

> = tWTR

CL = 3

RL = 5

NOP

DoutA0

Note: The minimum number of clock from the Burst Write command to the Burst Read command is [CL - 1 +

BL/2 + tWTR]. This tWTR is not a write recovery time (WR) but the time required to transfer the 4 bit write

data from the input buffer into sense amplifiers in the array.

Seamless Burst Write

< RL= 5; WL= 4; BL= 4 >

CLK

CMD

Posted CAS

WRITE A

NOP

Posted CAS

WRITE B

NOP

DQS,DQS

DQs

WL = RL-1 = 4

DinA0 DinA1 DinA2 DinA3 DinB0 DinB1 DinB2 DinB3

Note: The seamless burst write operation is supported by enabling a Write command at every other clock for BL

= 4 operation, and every 4 clock for BL = 8 operation. This operation is allowed regardless of same or

different banks as long as the banks are activated.

Elite Semiconductor Memory Technology Inc.

Publication Date : Jun. 2014

Revision : 1.0

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