M14D1G1664A-2S Datasheet, PDF (6/65 Pages) Elite Semiconductor Memory Technology Inc. – Internal pipelined double-data-rate architecture; two data access per clock cycle

ESMT
(Preliminary)
M14D1G1664A (2S)
Automotive Grade
DC Specifications
(IDD values are for the operation range of Voltage and Temperature)
Parameter
Symbol
Test Condition
Version
Unit
-1.8
-2.5
One bank;
Operating Current
(Active - Precharge)
IDD0
t_CK = t_CK (IDD), t_RC = t_RC (IDD), t_RAS = t_RAS (IDD)min;
CKE is High, CS is HIGH between valid commands;
60
Address bus inputs are SWITCHING;
Data bus inputs are SWITCHING
One bank; I_OUT = 0mA;
BL = 4, CL = CL(IDD), AL = 0;
Operating Current
t_CK = t_CK (IDD), t_RC = t_RC (IDD),
(Active - Read -
IDD1 t_RAS = t_RAS (IDD)min, t_RCD = t_RCD (IDD);
70
Precharge)
CKE is HIGH, CS is HIGH between valid commands;
Address bus inputs are SWITCHING;
Data pattern is same as IDD4W
All banks idle;
Precharge
Power-Down
Standby Current
IDD2P
t_CK = t_CK (IDD); CKE is LOW;
Other control and address bus inputs are STABLE;
10
Data bus inputs are FLOATING
All banks idle;
Precharge Quiet
Standby Current
IDD2Q
t_CK = t_CK (IDD); CKE is HIGH, CS is HIGH;
Other control and address bus inputs are STABLE;
35
Data bus inputs are FLOATING
All banks idle;
Idle Standby Current IDD2N
t_CK = t_CK (IDD); CKE is HIGH, CS is HIGH;
Other control and address bus inputs are SWITCHING;
40
Data bus inputs are SWITCHING
55
mA
65
mA
10
mA
35
mA
40
mA
Active Power-down
Standby Current
IDD3P
All banks open;
t_CK = t_CK (IDD); CKE is LOW;
Other control and address bus inputs
Fast PDN Exit
MRS(12) = 0
25
are STABLE;
Data bus input are FLOATING
Slow PDN Exit
MRS(12) = 1
15
Active Standby
Current
All banks open;
t_CK = t_CK (IDD), t_RAS = t_RAS (IDD)max, t_RP = t_RP (IDD);
IDD3N CKE is HIGH, CS is HIGH between valid commands;
43
Other control and address bus inputs are SWITCHING;
Data bus inputs are SWITCHING
All banks open, continuous burst Reads, I_OUT = 0mA;
BL = 4, CL = CL (IDD), AL = 0;
Operation Current
(Read)
IDD4R
t_CK = t_CK (IDD), t_RAS = t_RAS (IDD)max, t_RP = t_RP (IDD);
CKE is HIGH, CS is HIGH between valid commands;
140
Address bus inputs are SWITCHING;
Data pattern is the same as IDD4W;
All banks open, continuous burst Writes;
BL = 4, CL = CL (IDD), AL = 0;
Operation Current
(Write)
IDD4W
t_CK = t_CK (IDD), t_RAS = t_RAS (IDD)max, t_RP = t_RP (IDD);
CKE is HIGH, CS is HIGH between valid commands;
140
Address bus inputs are SWITCHING;
Data bus inputs are SWITCHING
25
mA
15
40
mA
130
mA
130
mA
Elite Semiconductor Memory Technology Inc.
Publication Date : Jul. 2014
Revision : 0.1
6/65