M14D1G1664A-2S Datasheet, PDF (16/65 Pages) Elite Semiconductor Memory Technology Inc. – Internal pipelined double-data-rate architecture; two data access per clock cycle

ESMT
(Preliminary)
M14D1G1664A (2S)
Automotive Grade
AC Timing Parameter & Specifications - Contiuned
Parameter
Symbol
-2.5
Min.
Max.
Unit Note
Minimum time clocks remains
ON after CKE asynchronously
t_DELAY t_IS + t_CK (avg)+t_IH
ns
drops low
Output impedance test driver
delay
t_OIT
0
12
ns
MRS command to ODT update
delay
t_MOD
0
12
ns
ODT turn-on delay
ODT turn-on
ODT turn-on (Power-Down
mode)
ODT turn-off delay
t_AOND
2
2
t_CK
t_AON
t_AC(min.) t_AC(max.) + 700 ps 14,16
2 x t_CK
t_AONPD tAC(min.) + 2000 +t_AC(max.) +
ps
1000
t_AOFD
2.5
2.5
t_CK
15,17
,18
ODT turn-off
ODT turn-off (Power-Down
mode)
ODT to Power-Down entry
latency
t_AOF
t_AC(min.) t_AC(max.) + 600 ps
2.5 x t_CK
t_AOFPD tAC(min.) + 2000 +t_AC(max.) +
ps
1000
t_ANPD
3
t_CK
ODT Power-Down exit latency
t_AXPD
8
t_CK
Note:
1. t_DAL[nCLK] = WR[nCLK] + tn_RP [nCLK] =WR+RU{t_RP[ps]/t_CK(avg)[ps]}, where WR is the value programmed in the mode
register set and RU status for round up.
2. AL: Additive Latency.
3. MRS A12 bit defines which Active Power-Down Exit timing to be applied.
4. The figures of Input Waveform Timing 1 and 2 are referenced from the input signal crossing at the VIH (AC) level for a rising
signal and VIL (AC) for a falling signal applied to the device under test.
5. The figures of Input Waveform Timing 1 and 2 are referenced from the input signal crossing at the VIL (DC) level for a rising
signal and VIH (DC) for a falling signal applied to the device under test.
6. t_HP is the minimum of the absolute half period of the actual input clock. t_HP is an input parameter but not an input
specification parameter. It is used in conjunction with t_QHS to derive the DRAM output timing t_QH. The value to be used for t_QH
calculation is determined by the following equation;
t_HP = Min ( t_CH (abs), t_CL (abs) ), where:
t_CH (abs) is the minimum of the actual instantaneous clock HIGH time;
t_CL (abs) is the minimum of the actual instantaneous clock LOW time;
7. t_QHS accounts for:
Elite Semiconductor Memory Technology Inc.
Publication Date : Jul. 2014
Revision : 0.1
16/65