English
Language : 

M14D1G1664A-2S Datasheet, PDF (35/65 Pages) Elite Semiconductor Memory Technology Inc. – Internal pipelined double-data-rate architecture; two data access per clock cycle
ESMT
(Preliminary)
M14D1G1664A (2S)
Automotive Grade
ODT Timing for Power-Down Mode
CLK
CLK
CKE
ODT
Internal
Term Res.
T0
T1
tIS
tAONPD(min.)
tAONPD(max.)
T2
T3
T4
tIS
tAOFPD(min.)
Rtt
T5
T6
tAOFPD(max.)
Elite Semiconductor Memory Technology Inc.
Publication Date : Jul. 2014
Revision : 0.1
35/65