M14D1G1664A-2S Datasheet, PDF(30/65 Page) Elite Semiconductor Memory Technology Inc. – Internal pipelined double-data-rate architecture; two data access per clock cycle

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M14D1G1664A-2S Datasheet, PDF (30/65 Pages) Elite Semiconductor Memory Technology Inc. – Internal pipelined double-data-rate architecture; two data access per clock cycle

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ESMT

(Preliminary)

Extended Mode Register Set-3 [EMRS(3)]

M14D1G1664A (2S)

Automotive Grade

BA2 BA1 BA0 A12 A11 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0

BA2 BA1 BA0

000

001

010

011

Mode Register

MRS

EMRS(1)

EMRS(2)

EMRS(3): Reserved

Note: EMRS(3) is reserved for future. All bits except BA0 and BA1 are reserved for future use and must be set to 0 when

setting to mode register during initialization.

Elite Semiconductor Memory Technology Inc.

Publication Date : Jul. 2014

Revision : 0.1

30/65

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