M14D1G1664A-2S Datasheet, PDF (59/65 Pages) Elite Semiconductor Memory Technology Inc. – Internal pipelined double-data-rate architecture; two data access per clock cycle

ESMT
(Preliminary)
M14D1G1664A (2S)
Automotive Grade
Current State
READ with
AUTO
PRECHARGE
WRITE with
AUTO
PRECHARGE
CS RAS CAS WE
H
X
X
X
L
H
H
H
L
H
L
H
L
H
L
L
L
L
H
H
L
L
H
L
L
L
L
H
L
L
L
L
H
X
X
X
L
H
H
H
L
H
L
H
L
H
L
L
L
L
H
H
L
L
H
L
L
L
L
H
L
L
L
L
H
X
X
X
L
H
H
H
L
H
L
X
PRE-CHARGIN
G
L
L
H
H
L
L
H
L
L
L
L
H
L
L
L
L
H
X
X
X
L
H
H
H
L
H
L
X
ROW
ACTIVATING L
L
H
H
L
L
H
L
L
L
L
H
L
L
L
L
Address
Command
Action
X
X
BA, CA, A10
BA, CA, A10
BA, RA
BA, A10 / A10
X
Op-Code Mode-Add
X
X
BA, CA, A10
BA, CA, A10
BA, RA
BA, A10
X
Op-Code Mode-Add
DESEL
NOP
READ / READA
WRITE / WRITEA
Active
PRE / PREA
Refresh
MRS / EMRS
DESEL
NOP
READ / READA
WRITE / WRITEA
Active
PRE / PREA
Refresh
MRS / EMRS
NOP (Continue Burst to end)
NOP (Continue Burst to end)
ILLEGAL (*1)
ILLEGAL (*1)
ILLEGAL (*1)
ILLEGAL (*1) / ILLEGAL
ILLEGAL
ILLEGAL
NOP (Continue Burst to END)
NOP (Continue Burst to END)
ILLEGAL (*1)
ILLEGAL (*1)
ILLEGAL (*1)
ILLEGAL (*1) / ILLEGAL
ILLEGAL
ILLEGAL
X
X
BA, CA, A10
BA, RA
BA, A10 / A10
X
Op-Code Mode-Add
DESEL
NOP (Idle after t_RP)
NOP
NOP (Idle after t_RP)
READ / READA /
WRITE / WRITEA
ILLEGAL (*1)
Active
ILLEGAL (*1)
PRE / PREA
Refresh
NOP (Idle after t_RP)
ILLEGAL
MRS / EMRS
ILLEGAL
X
X
BA, CA, A10
BA, RA
BA, A10 / A10
X
Op-Code Mode-Add
DESEL
NOP (Bank Active after t_RCD)
NOP
NOP (Bank Active after t_RCD)
READ / READA /
WRITE / WRITEA
ILLEGAL (*1, 5)
Active
ILLEGAL (*1)
PRE / PREA
ILLEGAL
Refresh
ILLEGAL
MRS / EMRS
ILLEGAL
Elite Semiconductor Memory Technology Inc.
Publication Date : Jul. 2014
Revision : 0.1
59/65