M14D1G1664A-2S Datasheet, PDF(33/65 Page) Elite Semiconductor Memory Technology Inc. – Internal pipelined double-data-rate architecture; two data access per clock cycle

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M14D1G1664A-2S Datasheet, PDF (33/65 Pages) Elite Semiconductor Memory Technology Inc. – Internal pipelined double-data-rate architecture; two data access per clock cycle

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ESMT

(Preliminary)

OCD Adjustable Mode

M14D1G1664A (2S)

Automotive Grade

CLK

Command EMRS(1)

DQS, DQS

NOP

tDS tDH

DT0 DT1 DT2 DT3

EMRS(1)

NOP

tWR

OCD adjustable

OCD calibration mode exit

Note: For proper operation of adjustable mode, WL = RL - 1 = AL + CL - 1 clocks and tDS / tDH should be met as the

above timing diagram. For input data pattern for adjustment, DT0 - DT3 is a fixed order and "not affected by

MRS addressing mode (ie. sequential or interleave).

CLK

Command EMRS(1)

High-Z

DQS, DQS

tOIT

OCD Driver Mode

NOP

EMRS(1)

DQs high and DQS low for Drive-1, DQs low and DQS high for Drive-0

High-Z

DQs high for Drive-1

DQs low for Drive-0

tOIT

Enter drive mode

OCD Calibration mode exit

Note: Drive mode, both Drive-1 and Drive-0, is used for controllers to measure DDR2 SDRAM driver impedance. In

this mode, all outputs are driven out tOIT after âenter drive modeâ command and all output drivers are

turned-off tOIT after âOCD calibration mode exitâ command as the above timing diagram.

Elite Semiconductor Memory Technology Inc.

Publication Date : Jul. 2014

Revision : 0.1

33/65

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