M14D1G1664A-2S Datasheet, PDF (49/65 Pages) Elite Semiconductor Memory Technology Inc. – Internal pipelined double-data-rate architecture; two data access per clock cycle

ESMT
(Preliminary)
M14D1G1664A (2S)
Automotive Grade
Write data mask by DM
One write data mask (DM) pin for each 8 data bits (DQ) will be supported on DDR2 SDRAM, Consistent with the implementation
on DDR2 SDRAM. It has identical timings on write operations as the data bits, and though used in a uni-directional manner, is
internally loaded identically to data bits to insure matched system timing. DM is not used during read cycles.
Data Mask Timing
T1
T2
T3
T4
T5
Tn
DQS
DQS
DQ
Din Din
Din Din
Din Din Din Din Din
DM
Write mask Iatency = 0
T0
CLK
CLK
Command
[tDQSS(min.)]
DQS,DQS
DQ
DM
[tDQSS(max.)]
DQS,DQS
DQ
DM
T1
WRIT
Example: < WL= 3; AL= 0; BL= 4 >
T2
T3
T4
T5
T6
NOP
WLt_DQSS
Din0
Din2
WL _tDQSS
Din0
Din2
T7
T8
tWR
Elite Semiconductor Memory Technology Inc.
Publication Date : Jul. 2014
Revision : 0.1
49/65