M14D1G1664A-2S Datasheet, PDF (10/65 Pages) Elite Semiconductor Memory Technology Inc. – Internal pipelined double-data-rate architecture; two data access per clock cycle

ESMT
(Preliminary)
M14D1G1664A (2S)
Automotive Grade
AC Operating Test Conditions
Parameter
Value
Unit
Note
Input reference voltage ( V_REF )
Input signal maximum peak swing ( V_SWING(max.) )
Input signal minimum slew rate
0.5 x V_DDQ
1.0
1.0
V
1
V
1
V/ns
2,3
Input level
V_IH / V_IL
V
Input timing measurement reference level
V_REF
V
Output timing measurement reference level (V_OTR)
0.5 x V_DDQ
V
4
Note:
1. Input waveform timing is referenced to the input signal crossing through the V_IH / V_IL (AC) level applied to the device under
test.
2. The input signal minimum slew rate is to be maintained over the range from V_REF to V_IH (AC) (min.) for rising edges and the
range from V_REF to V_IL (AC)(max.) for falling edges as shown in the below figure.
3. AC timings are referenced with input waveforms switching from V_IL (AC) to V_IH (AC) on the positive transitions and V_IH (AC) to
V_IL (AC) on the negative transitions.
4. The V_DDQ of the device under test is reference.
Elite Semiconductor Memory Technology Inc.
Publication Date : Jul. 2014
Revision : 0.1
10/65