M14D1G1664A-2S Datasheet, PDF (39/65 Pages) Elite Semiconductor Memory Technology Inc. – Internal pipelined double-data-rate architecture; two data access per clock cycle

ESMT
(Preliminary)
M14D1G1664A (2S)
Automotive Grade
Bank Active
The Bank Active command is issued by holding CAS and WE HIGH with CS and RAS LOW at the rising edge of the clock
(CLK). The DDR2 SDRAM has four independent banks, so two Bank Select addresses (BA0~BA2) are required. The Bank Active
command to the first Read or Write command must meet or exceed the minimum of RAS to CAS delay time (t_RCD(min.)). Once
a bank has been activated, it must be precharged before another Bank Active command can be applied to the same bank. The
minimum time interval between interleaved Bank Active command (Bank A to Bank B and vice versa) is the Bank to Bank delay
time (t_RRD min).
T0
CLK
CLK
Command
ACT
Bank Active Command Cycle
T1
T2
T3
Tn
Tn+1
Posted
READ
ACT
Posted
READ
PRE
Tn+2
Tn+3
PRE
ACT
Address
Bank A
Row Addr.
tRCD=1
Bank A
Col. Addr.
Bank B
Row Addr.
Bank B
Col. Addr.
Bank A
tCCD
Additive latency (AL)
Bank A Read begins
tRRD
tRAS
tRC
Bank A
Active
Bank B
Active
Bank A
Precharge
Bank B
Bank A
Row Addr.
tRP
Bank B Bank A
Precharge Active
Elite Semiconductor Memory Technology Inc.
Publication Date : Jul. 2014
Revision : 0.1
39/65