M14D1G1664A-2S Datasheet, PDF (38/65 Pages) Elite Semiconductor Memory Technology Inc. – Internal pipelined double-data-rate architecture; two data access per clock cycle

ESMT
(Preliminary)
M14D1G1664A (2S)
Automotive Grade
Precharge
The Precharge command is used to precharge or close a bank that has activated. The command is issued when CS , RAS and
WE are LOW and CAS is HIGH at the rising edge of the clock. The Precharge command can be used to precharge each bank
respectively or all banks simultaneously. The bank select addresses (BA0~BA2) and A10 are used to define which bank is
precharged when the command is initiated. For write cycle, t_WR(min.) must be satisfied until the Precharge command can be issued.
After t_RP from the precharge, a Bank Active command to the same bank can be initiated.
A10/AP
0
0
0
0
0
0
0
0
1
Bank Selection for Precharge by Address bits
BA2
BA1
BA0
0
0
0
0
1
0
0
0
1
0
1
1
1
0
0
1
1
0
1
0
1
1
1
1
X
X
X
Precharge
Bank A Only
Bank B Only
Bank C Only
Bank D Only
Bank E Only
Bank F Only
Bank G Only
Bank H Only
All Banks
NOP & Device Deselect
The device should be deselected by deactivating the CS signal. In this mode, DDR2 SDRAM would ignore all the control inputs.
The DDR2 SDRAM are put in NOP mode when CS is active and by deactivating RAS , CAS and WE . For both Deselect and
NOP, the device should finish the current operation when this command is issued.
Elite Semiconductor Memory Technology Inc.
Publication Date : Jul. 2014
Revision : 0.1
38/65