M-G362 Datasheet, PDF (20/69 Pages) Epson Company – IMU (Inertial Measurement Unit)

5.4 Data Output Timing
Data output rate: 2kSps
Average Filter TAP: N=2
500us
Delay from ADC's output to DRDY asserted.
< 300us
250us
ADC
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20
Filtering
Decimation &
Temp. Correction
DRDY signal
SPI_I/F
(Host reads data.)
1'
2'
3'
4'
5'
6'
7'
8'
9'
X(1')={X(1)+X(2)}/2
Figure 5.5 Data Output Timing – Data Output Rate 2kSps, Average Filter TAP N=2
Data output rate: 500Sps
Average Filter TAP: N=8
2ms
Delay from ADC's output to DRDY asserted.
< 300us
250us
ADC
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20
Filtering
Decimation &
Temp. Correction
DRDY signal
SPI_I/F
(Host reads data.)
1'
2'
X(1')={X(1)+X(2)+X(3)+X(4)+X(5)+X(6)+X(7)+X(8)}/8
Figure 5.6 Data Output Timing – Data Output Rate 500Sps, Average Filter TAP N=8
5.5 Data Ready Signal
The Data Ready signal is asserted when one sampling cycle completes and registers are updated with
new sensor values. When the sensor values are read out, the Data Ready signal becomes negated. In
case of UART AUTO mode, the Data Ready signal becomes negated just before data is output.
The Data Ready signal is output to the pin when the DRDY_ON (MSC_CTRL[0x02(W1)] bit[2]) is set to
“1”. The polarity of the signal can be changed by writing to the DRDY_POL of MSC_CTRL[0x02(W1)]
bit[1] register.
The Data Ready signal is the logical sum of all the ND flags corresponding to each sensor value. If all
the ND flags are disabled in the ND_EN (SIG_CTRL[0x00(W1)] bit[15:9]), the Data Ready will not be
asserted. On the other hand, if all the sensor values enabled in the ND_EN (SIG_CTRL[0x00(W1)]
bit[15:9]) are not read out, the Data Ready signal is kept asserted and never becomes negated.
Internal Sync
sampling
Data Ready
read data
16
Figure 5.7 Data Ready Signal Timing
Seiko Epson Corporation
M-G362PDC1 Data Sheet
Rev.20131217