PD45128441-I Datasheet, PDF (71/89 Pages) Elpida Memory – 128M-bit Synchronous DRAM 4-bank, LVTTL WTR (Wide Temperature Range)

13.21 Full Page Read Cycle (1/2) (/CAS Latency = 2)
T0 T1 T2 T3 T4 T5 T6 T7 Tn Tn + 1 Tn + 2 Tn + 3 Tn + 4 Tn + 5 Tn + 6 Tn + 7 Tn + 8 Tn + 9 Tn + 10 Tn + 11 Tn + 12 Tn + 13
CLK
CKE
H
/CS
/RAS
/CAS
/WE
BA0
BA1
A10
ADD
RAa
RAa
CAa
RDa
RDa
CDa
RDb
RDb
DQM
L
Hi-Z
DQ
Aa Aa+1 Aa+2 Aa-2 Aa-1 Aa Aa+1 Da Da+1 Da+2 Da+3 Da+4 Da+5 Da+6
Activate
Command
for Bank A
Read
Command
for Bank A
Activate
Command
for Bank D
Read
Command
for Bank D
Burst Stop Command
Precharge
Command
for Bank D
Activate
Command
for Bank D