PD45128441-I Datasheet, PDF (13/89 Pages) Elpida Memory – 128M-bit Synchronous DRAM 4-bank, LVTTL WTR (Wide Temperature Range)

µPD45128441-I, 45128841-I, 45128163-I
Self refresh entry command
(/CS, /RAS, /CAS, CKE = Low, /WE = High)
After the command execution, self refresh operation continues while
CKE remains low. When CKE goes high, the µPD45128xxx exits the
self refresh mode.
During self refresh mode, refresh interval and refresh operation are
performed internally, so there is no need for external control.
Before executing self refresh, all banks must be precharged.
Fig.7 Self refresh entry command
CLK
CKE
/CS
/RAS
/CAS
/WE
BA0(A13), BA1(A12)
A10
Add
Burst stop command
(/CS, /WE = Low, /RAS, /CAS = High)
This command can stop the current burst operation.
Fig.8 Burst stop command in Full Page
Mode
CLK
CKE _H
/CS
/RAS
/CAS
/WE
BA0(A13), BA1(A12)
A10
Add
No operation
(/CS = Low, /RAS, /CAS, /WE = High)
This command is not an execution command. No operations begin
or terminate by this command.
Fig.9 No operation
CLK
CKE _H
/CS
/RAS
/CAS
/WE
BA0(A13), BA1(A12)
A10
Add
Preliminary Data Sheet E0233N10
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