PD45128441-I Datasheet, PDF (11/89 Pages) Elpida Memory – 128M-bit Synchronous DRAM 4-bank, LVTTL WTR (Wide Temperature Range)

µPD45128441-I, 45128841-I, 45128163-I
2. Commands
Mode register set command
(/CS, /RAS, /CAS, /WE = Low)
The µPD45128xxx has a mode register that defines how the device
operates. In this command, A0 through A11, BA0(A13) and BA1(A12)
are the data input pins. After power on, the mode register set
command must be executed to initialize the device.
The mode register can be set only when all banks are in idle state.
During 2 CLK (tRSC) following this command, the µPD45128xxx
cannot accept any other commands.
Fig.1 Mode register set command
CLK
CKE _H
/CS
/RAS
/CAS
/WE
BA0(A13), BA1(A12)
A10
Add
Activate command
(/CS, /RAS = Low, /CAS, /WE = High)
The µPD45128xxx has four banks, each with 4,096 rows.
This command activates the bank selected by BA0(A13) and
BA1(A12) and a row address selected by A0 through A11.
This command corresponds to a conventional DRAM’s /RAS falling.
Fig.2 Row address strobe and
bank activate command
CLK
CKE
/CS
/RAS
/CAS
/WE
BA0(A13), BA1(A12)
A10
Add
H
Row
Row
Precharge command
(/CS, /RAS, /WE = Low, /CAS = High)
This command begins precharge operation of the bank selected by
BA0(A13) and BA1(A12). When A10 is High, all banks are
precharged, regardless of BA0(A13) and BA1(A12). When A10 is
Low, only the bank selected by BA0(A13) and BA1(A12) is
precharged.
After this command, the µPD45128xxx can’t accept the activate
command to the precharging bank during tRP (precharge to activate
command period).
This command corresponds to a conventional DRAM’s /RAS rising.
Fig.3 Precharge command
CLK
CKE _H
/CS
/RAS
/CAS
/WE
BA0(A13), BA1(A12)
A10
(Precharge select)
Add
Preliminary Data Sheet E0233N10
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