PD45128441-I Datasheet, PDF (38/89 Pages) Elpida Memory – 128M-bit Synchronous DRAM 4-bank, LVTTL WTR (Wide Temperature Range)

µPD45128441-I, 45128841-I, 45128163-I
Asynchronous Characteristics
Parameter
Symbol
-A 75
-A 80
-A 10
Unit
MIN. MAX. MIN. MAX. MIN. MAX.
ACT to REF/ACT command period (operation) tRC 67.5
70
70
ns
REF to REF/ACT command period (refresh) tRC1 67.5
70
70
ns
ACT to PRE command period
tRAS
45 120,000 48 120,000 50 120,000 ns
PRE to ACT command period
tRP
20
20
20
ns
Delay time ACT to READ/WRITE command tRCD 20
20
20
ns
ACT (one) to ACT (another) command period tRRD 15
16
20
ns
Data-in to PRE command period
tDPL
15
15
15
ns
Data-in to ACT (REF)
/CAS latency = 3 tDAL3 1CLK
1CLK
1CLK
ns
command period
+22.5
+20
+20
(Auto precharge)
/CAS latency = 2 tDAL2 1CLK
1CLK
1CLK
ns
+20
+20
+20
Mode register set cycle time
tRSC
2
2
2
CLK
Transition time
tT
0.5
30
0.5
30
1
30
ns
Refresh time (4,096 refresh cycles)
tREF
64
64
64
ms
Note
1
Note 1. The –A75 grade device can satisfy the tDAL3 spec of 1CLK+20 ns for up to and including 125MHz operation.
38
Preliminary Data Sheet E0233N10