PD45128441-I Datasheet, PDF (52/89 Pages) Elpida Memory – 128M-bit Synchronous DRAM 4-bank, LVTTL WTR (Wide Temperature Range)

13.11 Self Refresh (Entry and Exit)
T0 T1 T2 T3 T4
CLK
CKE
/CS
/RAS
/CAS
/WE
BA0
BA1
A10
ADD
DQM
L
Hi-Z
DQ
Precharge Self Refresh
Command
Entry
(if necessary)
tRP
Tn Tn + 1 Tn + 2
Tm Tm + 1
Tk Tk + 1 Tk + 2 Tk + 3 Tk + 4
Self Refresh
Exit
Self Refresh Self Refresh
Entry
Exit
(or Activate Command)
Next Clock
Enable
tRC1
Activate
Command
Next Clock
Enable
tRC1