PD45128441-I Datasheet, PDF (37/89 Pages) Elpida Memory – 128M-bit Synchronous DRAM 4-bank, LVTTL WTR (Wide Temperature Range)

µPD45128441-I, 45128841-I, 45128163-I
Synchronous Characteristics
Parameter
Symbol
-A 75
-A 80
-A 10
Unit
MIN. MAX. MIN. MAX. MIN. MAX.
Clock cycle time
/CAS latency = 3 tCK3
/CAS latency = 2 tCK2
Access time from CLK
/CAS latency = 3 tAC3
/CAS latency = 2 tAC2
CLK high level width
tCH
CLK low level width
tCL
Data-out hold time
tOH
Data-out low-impedance time
tLZ
Data-out high-impedance time /CAS latency = 3 tHZ3
/CAS latency = 2 tHZ2
Data-in setup time
tDS
Data-in hold time
tDH
Address setup time
tAS
Address hold time
tAH
CKE setup time
tCKS
CKE hold time
tCKH
CKE setup time (Power down exit)
tCKSP
Command (/CS, /RAS, /CAS, /WE, DQM) tCMS
setup time
Command (/CS, /RAS, /CAS, /WE, DQM) tCMH
hold time
7.5 (133 MHz) 8 (125 MHz) 10 (100 MHz) ns
10 (100 MHz) 10 (100 MHz) 13 (77 MHz) ns
5.4
6
6
ns
6
6
7
ns
2.5
3
3
ns
2.5
3
3
ns
2.7
2.7
2.7
ns
0
0
0
ns
2.7
5.4
2.7
6
2.7
6
ns
2.7
6
2.7
6
2.7
7
ns
1.5
2
2
ns
0.8
1
1
ns
1.5
2
2
ns
0.8
1
1
ns
1.5
2
2
ns
0.8
1
1
ns
1.5
2
2
ns
1.5
2
2
ns
0.8
1
1
ns
Note 1. Output load
Note
1
1
1
Output
Z = 50 Ω
50 pF
Preliminary Data Sheet E0233N10
37