PD45128441-I Datasheet, PDF (44/89 Pages) Elpida Memory – 128M-bit Synchronous DRAM 4-bank, LVTTL WTR (Wide Temperature Range)

13.5 Power On Sequence and CBR (Auto) Refresh
CLK
Clock cycle is necessary
CKE
High level is necessary
tRSC
/CS
/RAS
/CAS
/WE
BA0
BA1
A10
ADD
ADDRESS KEY
DQM
DQ
High level is necessary
Hi-Z
Precharge
All Banks
Command
is necessary
Mode
Register Set
Command
is necessary
CBR (Auto)
Refresh
Command
is necessary
tRP
2 refresh cycles are necessary
CBR (Auto)
Refresh
Command
is necessary
tRC1
Activate
Command
tRC1