S6E1C3 Datasheet, PDF (98/107 Pages) Cypress Semiconductor – 32-bit ARM® Cortex®-M0+ FM0+ Microcontroller

S6E1C3 Series
Operation Example of Return from Low Power Consumption Mode (by Internal Resource Reset*)
Internal
resource
reset
Internal reset
Reset active
t_RCNT
Release
CPU
Operation
Start
*: Internal resource reset is not included in return factor by the kind of Low-Power consumption mode.
Notes:
− The return factor is different in each Low-Power consumption modes.
See "Chapter: Low Power Consumption Mode" and "Operations of Standby Modes" in FM0+ Family Peripheral Manual.
− When interrupt recoveries, the operation mode that CPU recoveries depends on the state before the Low-Power consumption
mode transition. See "Chapter: Low Power Consumption Mode" in "FM0+ Family Peripheral Manual".
− The time during the power-on reset/low-voltage detection reset is excluded. See "11.4.7 Power-on Reset Timing in 11.4 AC
Characteristics in 11. Electrical Characteristics" for the detail on the time during the power-on reset/low -voltage detection
reset.
− When in recovery from reset, CPU changes to the high-speed CR run mode. When using the main clock or the PLL clock, it is
necessary to add the main clock oscillation stabilization wait time or the main PLL clock stabilization wait time.
− The internal resource reset means the watchdog reset and the CSV reset.
Document Number: 002-00233 Rev.*B
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