S6E1C3 Datasheet, PDF (79/107 Pages) Cypress Semiconductor – 32-bit ARM® Cortex®-M0+ FM0+ Microcontroller

S6E1C3 Series
11.4.11 I²C Timing / I2C Slave Timing
(VCC= 1.65 V to 3.6 V, VSS= 0 V, TA=- 40°C to +105°C)
Parameter
Symbo
l
Conditions
Standard-Mode
Min Max
Fast-Mode
Min
Max
Unit
Remarks
SCL(SI2CSCL) clock frequency
FSCL
0
100
0
400 kHz
(Repeated) Start condition hold time
SDA(SI2CSDA) ↓ → SCL(SI2CSCL)
↓
tHDSTA
4.0
-
0.6
-
μs
SCL(SI2CSCL) clock L width
tLOW
4.7
-
1.3
-
μs
SCL(SI2CSCL) clock H width
tHIGH
4.0
-
0.6
-
μs
(Repeated) Start setup time
SCL(SI2CSCL) ↑ → SDA
(SI2CSDA) ↓
tSUSTA
4.7
-
0.6
-
μs
Data hold time
SCL(SI2CSCL) ↓ → SDA(SI2CSDA)
↓↑
tHDDAT
CL=30 pF,
R=(Vp/IOL)*¹
0
3.45*²
0
0.9*³ μs
Data setup time
SDA (SI2CSDA)↓ ↑ → SCL
(SI2CSCL)↑
tSUDAT
250
-
100
-
ns
Stop condition setup time
SCL(SI2CSCL) ↑ → SDA(SI2CSDA)
↑
tSUSTO
4.0
-
0.6
-
μs
Bus free time between
Stop condition and
tBUF
Start condition
4.7
-
1.3
-
μs
Noise filter
tSP
-
2
tCYCP*⁴
-
2
tCYCP*⁴
-
ns
except I2C
Slave
*1: R represents the pull-up resistance of the SCL and SDA lines, and CL the load capacitance of the SCL and SDA lines. VP
represents the power supply voltage of the pull-up resistance, and IOL the VOL guaranteed current.
*2: The maximum tHDDAT must satisfy at least the condition that the period during which the device is holding the SCL signal at L
(tLOW) does not extend.
*3: A Fast-mode I²C bus device can be used in a Standard-mode I²C bus system, provided that the condition of tSUDAT ≥ 250 ns is
fulfilled.
*4: tCYCP represents the APB bus clock cycle time.
For the number of the APB bus to which the I²C is connected, see "8. Block Diagram".
To use Standard-mode, set the APB bus clock at 2 MHz or more.
To use Fast-mode, set the APB bus clock at 8 MHz or more.
SDA
SCL
tLOW
tSUDAT
tHDSTA
tHDDAT
tHIGH
tSUSTA
tHDSTA
tBUF
tSP
tSUSTO
Document Number: 002-00233 Rev.*B
Page 79 of 107