S6E1C3 Datasheet, PDF (58/107 Pages) Cypress Semiconductor – 32-bit ARM® Cortex®-M0+ FM0+ Microcontroller

S6E1C3 Series
11.4.4 Operating Conditions of Main PLL
(In the Case of Using the Main Clock as the Input Clock of the PLL)
(VCC= 1.65 V to 3.6 V, VSS= 0 V, TA=- 40°C to +105°C)
Parameter
Value
Symbol
Unit
Min Typ Max
Remarks
PLL oscillation stabilization wait time*¹
(LOCK UP time)
tLOCK
50
-
-
μs
PLL input clock frequency
FPLLI
8
-
PLL multiple rate
-
5
-
PLL macro oscillation clock frequency
Main PLL clock frequency*²
USB clock frequency*³
FPLLO
75
-
FCLKPLL
-
-
FCLKSPLL
-
-
*1: The wait time is the time it takes for PLL oscillation to stabilize.
16
MHz
18 multiple
150 MHz
40
MHz
48
MHz
*2: For details of the main PLL clock (CLKPLL), refer to "Chapter: Clock" in "FM0+ Family Peripheral Manual".
*3: For more information about USB clock, see "Chapter: USB Clock Generation" in "FM0+ Family Peripheral Manual
Communication Macro Part”.
Main PLL connection
Main clock (CLKMO)
High-speed CR clock (CLKHC)
PLL input
K ^clock
divider
Main
PLL
PLL macro
oscillation clock _M
divider
Main PLL
clock
(CLKPLL)
N
divider
USB
clock
divider
USB clock
11.4.5 Operating Conditions of Main PLL
(In the Case of Using the Built-in High-Speed CR Clock as the Input Clock of the Main PLL)
(VCC= 1.65 V to 3.6 V, VSS= 0 V, TA=- 40°C to +105°C)
Parameter
Value
Symbol
Unit
Min Typ Max
Remarks
PLL oscillation stabilization wait time*¹
(LOCK UP time)
tLOCK
50
-
-
μs
PLL input clock frequency
FPLLI
7.84
8
8.16
MHz
PLL multiple rate
-
9
-
18
multiple
PLL macro oscillation clock frequency
Main PLL clock frequency*²
FPLLO
75
FCLKPLL
-
-
150
-
40.8
MHz
MHz
*1: The wait time is the time it takes for PLL oscillation to stabilize.
*2: For details of the main PLL clock (CLKPLL), refer to "Chapter: Clock" in "FM0+ Family Peripheral Manual".
Note:
Document Number: 002-00233 Rev.*B
Page 58 of 107